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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Marcel Ziswiler90392d02016-11-14 21:40:26 +01002/*
3 * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marcel Ziswiler90392d02016-11-14 21:40:26 +01004 */
5
6#ifndef __SERIAL_PXA_H
7#define __SERIAL_PXA_H
8
9/*
10 * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
11 * easily handle enabling of clock.
12 */
13#ifdef CONFIG_CPU_MONAHANS
14#define UART_CLK_BASE CKENA_21_BTUART
15#define UART_CLK_REG CKENA
16#define BTUART_INDEX 0
17#define FFUART_INDEX 1
18#define STUART_INDEX 2
19#elif CONFIG_CPU_PXA25X
20#define UART_CLK_BASE (1 << 4) /* HWUART */
21#define UART_CLK_REG CKEN
22#define HWUART_INDEX 0
23#define STUART_INDEX 1
24#define FFUART_INDEX 2
25#define BTUART_INDEX 3
26#else /* PXA27x */
27#define UART_CLK_BASE CKEN5_STUART
28#define UART_CLK_REG CKEN
29#define STUART_INDEX 0
30#define FFUART_INDEX 1
31#define BTUART_INDEX 2
32#endif
33
34/*
35 * Only PXA250 has HWUART, to avoid poluting the code with more macros,
36 * artificially introduce this.
37 */
38#ifndef CONFIG_CPU_PXA25X
39#define HWUART_INDEX 0xff
40#endif
41
42/*
43 * struct pxa_serial_platdata - information about a PXA port
44 *
45 * @base: Uart port base register address
46 * @port: Uart port index, for cpu with pinmux for uart / gpio
47 * baudrtatre: Uart port baudrate
48 */
49struct pxa_serial_platdata {
50 struct pxa_uart_regs *base;
51 int port;
52 int baudrate;
53};
54
55#endif /* __SERIAL_PXA_H */