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git01.mediatek.com / filogic / uboot / 72cc53897fd104911dff82aefc3624757ebcecd0 / . / configs / T2080RDB_revD_SPIFLASH_defconfig
blob: cf4bf315a3a70852509e84a3d1c776dabb906cd7 [file] [log] [blame]
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]1CONFIG_PPC=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame^]2CONFIG_TEXT_BASE=0x00200000
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]3CONFIG_SPL_LIBCOMMON_SUPPORT=y
4CONFIG_SPL_LIBGENERIC_SUPPORT=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]5CONFIG_ENV_SIZE=0x2000
6CONFIG_ENV_OFFSET=0x100000
7CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]9CONFIG_SPL_TEXT_BASE=0xFFFD8000
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]10CONFIG_SPL_SERIAL=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]11CONFIG_SPL_DRIVERS_MISC=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]12CONFIG_SPL=y
13CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]14CONFIG_SPL_SPI=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]15CONFIG_MPC85xx=y
16CONFIG_TARGET_T2080RDB=y
Tom Rinia7fa9762022-06-15 12:03:45 -0400[diff] [blame]17CONFIG_ENABLE_36BIT_PHYS=y
Tom Rini2daaf642022-06-25 11:02:43 -0400[diff] [blame]18CONFIG_SYS_BOOK3E_HV=y
Tom Rini41e1a592022-06-27 13:35:46 -0400[diff] [blame]19CONFIG_SYS_CACHE_STASHING=y
Tom Rini667dd4f2022-06-10 22:59:37 -0400[diff] [blame]20CONFIG_SYS_MPC85XX_NO_RESETVEC=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]21CONFIG_T2080RDB_REV_D=y
Tom Rini7485ebf62022-06-20 08:07:45 -0400[diff] [blame]22CONFIG_PCIE1=y
23CONFIG_PCIE2=y
24CONFIG_PCIE3=y
25CONFIG_PCIE4=y
26CONFIG_VID=y
27CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
28CONFIG_VOL_MONITOR_IR36021_READ=y
29CONFIG_VOL_MONITOR_IR36021_SET=y
Tom Rinibc7b0df2022-07-31 21:08:27 -0400[diff] [blame]30CONFIG_SYS_FSL_NUM_CC_PLLS=2
Tom Rini76fbc6f2022-04-01 10:33:18 -0400[diff] [blame]31CONFIG_SYS_MEMTEST_START=0x00200000
32CONFIG_SYS_MEMTEST_END=0x00400000
Tom Rini5ca768d2022-01-24 21:08:41 +0000[diff] [blame]33CONFIG_MP=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]34CONFIG_FIT=y
35CONFIG_FIT_VERBOSE=y
36CONFIG_OF_BOARD_SETUP=y
37CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rini9ff815a2021-08-24 23:11:49 -0400[diff] [blame]38CONFIG_RAMBOOT_PBL=y
Tom Rini886e6e32022-03-23 17:20:03 -0400[diff] [blame]39CONFIG_SPIFLASH=y
Tom Rini9ff815a2021-08-24 23:11:49 -0400[diff] [blame]40CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
41CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]42CONFIG_BOOTDELAY=10
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]43CONFIG_USE_BOOTCOMMAND=y
44CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
Tom Rinif05f9d82022-04-13 09:14:57 -0400[diff] [blame]45CONFIG_ARCH_MISC_INIT=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]46CONFIG_BOARD_EARLY_INIT_R=y
47# CONFIG_SPL_FRAMEWORK is not set
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]48CONFIG_SPL_MAX_SIZE=0x28000
49CONFIG_SPL_PAD_TO=0x40000
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]50CONFIG_SPL_SPI_BOOT=y
51CONFIG_SPL_FSL_PBL=y
Tom Rini17845c52022-05-21 11:26:27 -0400[diff] [blame]52CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
Tom Rini6b15c162022-05-13 12:26:35 -0400[diff] [blame]53CONFIG_SPL_FLUSH_IMAGE=y
54CONFIG_SPL_SKIP_RELOCATE=y
Tom Rinid75a7792022-05-27 16:19:05 -0400[diff] [blame]55CONFIG_SPL_GD_ADDR=0xfffc8000
Tom Rini6de36a72022-05-26 16:59:30 -0400[diff] [blame]56CONFIG_SPL_RELOC_STACK=0xfffd8000
57CONFIG_SPL_RELOC_MALLOC=y
58CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000
59CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]60CONFIG_SPL_ENV_SUPPORT=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]61CONFIG_SPL_I2C=y
Simon Glass64571062021-08-08 12:20:16 -0600[diff] [blame]62CONFIG_SPL_MPC8XXX_INIT_DDR=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]63CONFIG_HUSH_PARSER=y
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]64CONFIG_SYS_PBSIZE=276
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]65CONFIG_CMD_IMLS=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]66CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]67CONFIG_CMD_MEMTEST=y
68CONFIG_SYS_ALT_MEMTEST=y
69CONFIG_CMD_DM=y
70CONFIG_CMD_I2C=y
71CONFIG_CMD_MMC=y
72CONFIG_CMD_USB=y
73CONFIG_CMD_DHCP=y
74CONFIG_CMD_MII=y
75CONFIG_CMD_PING=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]76CONFIG_CMD_EXT2=y
77CONFIG_CMD_FAT=y
78CONFIG_CMD_MTDPARTS=y
79CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
80CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
81# CONFIG_CMD_IRQ is not set
82CONFIG_OF_CONTROL=y
83CONFIG_ENV_OVERWRITE=y
84CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rini5fb860c2022-02-25 11:19:48 -0500[diff] [blame]85CONFIG_USE_BOOTFILE=y
86CONFIG_BOOTFILE="uImage"
Tom Rinife586752022-03-11 09:12:07 -0500[diff] [blame]87CONFIG_USE_ETHPRIME=y
88CONFIG_ETHPRIME="FM1@DTSEC3"
Tom Rini276d75e2022-06-10 22:59:27 -0400[diff] [blame]89CONFIG_FSL_SATA_V2=y
Simon Glass231e7742022-01-31 07:49:37 -0700[diff] [blame]90CONFIG_SYS_SATA_MAX_DEVICE=2
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]91CONFIG_FSL_CAAM=y
Tom Rinif7246c22021-08-21 13:50:17 -0400[diff] [blame]92CONFIG_DDR_CLK_FREQ=133330000
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]93CONFIG_DDR_ECC=y
94CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]95CONFIG_DM_I2C=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]96CONFIG_SPL_SYS_I2C_LEGACY=y
Tom Rinib1b13072021-08-18 23:12:37 -0400[diff] [blame]97CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
Tom Rinibe94c762021-08-18 23:12:35 -0400[diff] [blame]98CONFIG_SYS_I2C_FSL=y
99CONFIG_SYS_FSL_I2C_OFFSET=0x118000
100CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
101CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
102CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
103CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
104CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
105CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]106CONFIG_SYS_I2C_EEPROM_ADDR=0x50
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]107CONFIG_FSL_ESDHC=y
108CONFIG_MTD=y
109CONFIG_MTD_NOR_FLASH=y
110CONFIG_FLASH_CFI_DRIVER=y
111CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
Tom Rini302bd672022-07-23 13:04:55 -0400[diff] [blame]112CONFIG_SYS_FLASH_EMPTY_INFO=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]113CONFIG_FLASH_CFI_MTD=y
114CONFIG_SYS_FLASH_CFI=y
Tom Rini2e35d822022-07-23 13:05:05 -0400[diff] [blame]115CONFIG_SYS_FLASH_QUIET_TEST=y
Tom Rinid38112c2022-07-23 13:05:04 -0400[diff] [blame]116CONFIG_SYS_MAX_FLASH_SECT=1024
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]117CONFIG_DM_SPI_FLASH=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]118CONFIG_SF_DEFAULT_SPEED=10000000
119CONFIG_SPI_FLASH_STMICRO=y
120CONFIG_PHYLIB=y
121CONFIG_PHY_AQUANTIA=y
122CONFIG_PHY_CORTINA=y
123CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
Kuldeep Singh016965f2021-08-10 11:20:07 +0530[diff] [blame]124CONFIG_CORTINA_FW_ADDR=0x120000
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]125CONFIG_PHY_REALTEK=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]126CONFIG_DM_MDIO=y
127CONFIG_E1000=y
128CONFIG_FMAN_ENET=y
Rajesh Bhagataec38012021-11-09 16:30:38 +0530[diff] [blame]129CONFIG_SYS_FMAN_FW_ADDR=0x110000
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]130CONFIG_MII=y
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]131CONFIG_DM_PCI_COMPAT=y
132CONFIG_PCIE_FSL=y
133CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
134CONFIG_DM_RTC=y
135CONFIG_RTC_DS1307=y
136CONFIG_SYS_NS16550=y
137CONFIG_SPI=y
138CONFIG_DM_SPI=y
139CONFIG_FSL_ESPI=y
140CONFIG_USB=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]141CONFIG_USB_EHCI_FSL=y
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]142CONFIG_USB_MAX_CONTROLLER_COUNT=2
Camelia Groza9bf4db62021-06-11 15:28:08 +0300[diff] [blame]143CONFIG_USB_STORAGE=y
144CONFIG_ADDR_MAP=y
145CONFIG_SYS_NUM_ADDR_MAP=64