blob: 9a77b7bcbc73436f4eb1498d14ebc7a462f0765b [file] [log] [blame]
Jon Loeliger3e2d0912007-04-11 16:50:57 -05001/*
2 * Copyright 2007 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8544ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/* High Level Configuration Options */
31#define CONFIG_BOOKE 1 /* BOOKE */
32#define CONFIG_E500 1 /* BOOKE e500 family */
33#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34#define CONFIG_MPC8544 1
35#define CONFIG_MPC8544DS 1
36
Ed Swarthout52b98522007-07-27 01:50:51 -050037#define CONFIG_PCI 1 /* Enable PCI/PCIE */
38#define CONFIG_PCI1 1 /* PCI controller 1 */
39#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
40#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
41#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
42#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala93166d22007-12-07 12:17:34 -060043#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050044
Kumar Gala85af2b52008-01-16 01:16:16 -060045#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
46
Ed Swarthout52b98522007-07-27 01:50:51 -050047#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050048#define CONFIG_ENV_OVERWRITE
49#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
50#undef CONFIG_DDR_DLL
51#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
52
53#define CONFIG_DDR_ECC /* only for ECC DDR module */
54#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
55#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
56
57#define CONFIG_DDR_ECC_CMD
Ed Swarthout52b98522007-07-27 01:50:51 -050058#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050059
60/*
61 * When initializing flash, if we cannot find the manufacturer ID,
62 * assume this is the AMD flash associated with the CDS board.
63 * This allows booting from a promjet.
64 */
65#define CONFIG_ASSUME_AMD_FLASH
66
67#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
68
69#ifndef __ASSEMBLY__
70extern unsigned long get_board_sys_clk(unsigned long dummy);
71#endif
72#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
73
74/*
75 * These can be toggled for performance analysis, otherwise use default.
76 */
Ed Swarthout52b98522007-07-27 01:50:51 -050077#define CONFIG_L2_CACHE /* toggle L2 cache */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050078#define CONFIG_BTB /* toggle branch predition */
79#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050080
81/*
82 * Only possible on E500 Version 2 or newer cores.
83 */
84#define CONFIG_ENABLE_36BIT_PHYS 1
85
Jon Loeliger3e2d0912007-04-11 16:50:57 -050086#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
87#define CFG_MEMTEST_END 0x00400000
Ed Swarthout52b98522007-07-27 01:50:51 -050088#define CONFIG_PANIC_HANG /* do not reset board on panic */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050089
90/*
91 * Base addresses -- Note these are effective addresses where the
92 * actual resources get mapped (not physical addresses)
93 */
Ed Swarthout52b98522007-07-27 01:50:51 -050094#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050095#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
Kumar Galad33a55f2008-01-30 14:55:14 -060096#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050097#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
98
99#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
100#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
101#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000)
102#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000)
103
104/*
105 * DDR Setup
106 */
107#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
108#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
109
110#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
111
112/*
113 * Make sure required options are set
114 */
115#ifndef CONFIG_SPD_EEPROM
116#error ("CONFIG_SPD_EEPROM is required")
117#endif
118
119#undef CONFIG_CLOCKS_IN_MHZ
120
121/*
122 * Memory map
123 *
124 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
125 *
126 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
127 *
128 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
129 *
130 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
131 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
132 *
133 * Localbus cacheable
134 *
135 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
136 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
137 *
138 * Localbus non-cacheable
139 *
140 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
141 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
142 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
143 *
144 */
145
146/*
147 * Local Bus Definitions
148 */
149#define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */
150
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500151#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
152
153#define CFG_BR0_PRELIM 0xff801001
154#define CFG_BR1_PRELIM 0xfe801001
155
156#define CFG_OR0_PRELIM 0xff806e65
157#define CFG_OR1_PRELIM 0xff806e65
158
Andy Flemingd4cba1e2008-07-14 20:26:57 -0500159#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500160
Roy Zangfd2896b2008-04-25 00:55:09 -0500161#define CFG_FLASH_QUIET_TEST
Andy Flemingd4cba1e2008-07-14 20:26:57 -0500162#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500163#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
164#undef CFG_FLASH_CHECKSUM
165#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
166#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Galaded59a12008-06-09 18:55:38 -0500167#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500168
169#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
170
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200171#define CONFIG_FLASH_CFI_DRIVER
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500172#define CFG_FLASH_CFI
173#define CFG_FLASH_EMPTY_INFO
174
175#define CFG_LBC_NONCACHE_BASE 0xf8000000
176
177#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
178#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
179
180#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
181#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
182
Kim Phillips53b34982007-08-21 17:00:17 -0500183#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500184#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
185#define PIXIS_ID 0x0 /* Board ID at offset 0 */
186#define PIXIS_VER 0x1 /* Board version at offset 1 */
187#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
188#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
189#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
190 * register */
191#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
192#define PIXIS_VCTL 0x10 /* VELA Control Register */
193#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
194#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
195#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
196#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
197#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
198#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
199#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jason Jinf08899a2007-10-29 19:26:21 +0800200#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500201
202
203/* define to use L1 as initial stack */
Andy Flemingb4b02c02008-07-14 20:29:07 -0500204#define CONFIG_L1_INIT_RAM
205#define CFG_INIT_RAM_LOCK 1
206#define CFG_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
207#define CFG_INIT_RAM_END 0x00004000 /* End of used area in RAM */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500208
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500209
210#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
211#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
212#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
213
214#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
Kumar Gala559e5312008-07-14 14:07:03 -0500215#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500216
217/* Serial Port - controlled on board with jumper J8
218 * open - index 2
219 * shorted - index 1
220 */
221#define CONFIG_CONS_INDEX 1
222#undef CONFIG_SERIAL_SOFTWARE_FIFO
223#define CFG_NS16550
224#define CFG_NS16550_SERIAL
225#define CFG_NS16550_REG_SIZE 1
226#define CFG_NS16550_CLK get_bus_freq(0)
227
228#define CFG_BAUDRATE_TABLE \
229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
230
231#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
232#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
233
234/* Use the HUSH parser */
235#define CFG_HUSH_PARSER
236#ifdef CFG_HUSH_PARSER
237#define CFG_PROMPT_HUSH_PS2 "> "
238#endif
239
240/* pass open firmware flat tree */
Kumar Gala67b349b2007-11-26 17:12:24 -0600241#define CONFIG_OF_LIBFDT 1
242#define CONFIG_OF_BOARD_SETUP 1
243#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500244
245/* I2C */
246#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
247#define CONFIG_HARD_I2C /* I2C with hardware support */
248#undef CONFIG_SOFT_I2C /* I2C bit-banged */
249#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
250#define CFG_I2C_EEPROM_ADDR 0x57
251#define CFG_I2C_SLAVE 0x7F
252#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
253#define CFG_I2C_OFFSET 0x3100
254
255/*
256 * General PCI
257 * Memory space is mapped 1-1, but I/O space must start from 0.
258 */
259#define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
260#define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
261
262#define CFG_PCI1_MEM_BASE 0xc0000000
263#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
264#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
265#define CFG_PCI1_IO_BASE 0x00000000
266#define CFG_PCI1_IO_PHYS 0xe1000000
Kumar Galaace11d82007-08-16 15:05:04 -0500267#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500268
269/* PCI view of System Memory */
270#define CFG_PCI_MEMORY_BUS 0x00000000
271#define CFG_PCI_MEMORY_PHYS 0x00000000
272#define CFG_PCI_MEMORY_SIZE 0x80000000
273
274/* controller 2, Slot 1, tgtid 1, Base address 9000 */
275#define CFG_PCIE2_MEM_BASE 0x80000000
276#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
277#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
278#define CFG_PCIE2_IO_BASE 0x00000000
Kumar Galaace11d82007-08-16 15:05:04 -0500279#define CFG_PCIE2_IO_PHYS 0xe1010000
280#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500281
282/* controller 1, Slot 2,tgtid 2, Base address a000 */
283#define CFG_PCIE1_MEM_BASE 0xa0000000
284#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
Kumar Galaace11d82007-08-16 15:05:04 -0500285#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */
286#define CFG_PCIE1_IO_BASE 0x00000000
287#define CFG_PCIE1_IO_PHYS 0xe1020000
288#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500289
290/* controller 3, direct to uli, tgtid 3, Base address b000 */
291#define CFG_PCIE3_MEM_BASE 0xb0000000
292#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
Kumar Galaace11d82007-08-16 15:05:04 -0500293#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500294#define CFG_PCIE3_IO_BASE 0x00000000
Kumar Galaace11d82007-08-16 15:05:04 -0500295#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500296#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
Kumar Galae1e870a2007-08-30 16:18:18 -0500297#define CFG_PCIE3_MEM_BASE2 0xb0200000
298#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
299#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500300
301#if defined(CONFIG_PCI)
302
Kumar Gala559e5312008-07-14 14:07:03 -0500303/*PCIE video card used*/
304#define VIDEO_IO_OFFSET CFG_PCIE2_IO_PHYS
305
306/*PCI video card used*/
307/*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/
308
309/* video */
310#define CONFIG_VIDEO
311
312#if defined(CONFIG_VIDEO)
313#define CONFIG_BIOSEMU
314#define CONFIG_CFB_CONSOLE
315#define CONFIG_VIDEO_SW_CURSOR
316#define CONFIG_VGA_AS_SINGLE_DEVICE
317#define CONFIG_ATI_RADEON_FB
318#define CONFIG_VIDEO_LOGO
319/*#define CONFIG_CONSOLE_CURSOR*/
320#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
321#endif
322
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500323#define CONFIG_NET_MULTI
324#define CONFIG_PCI_PNP /* do pci plug-and-play */
325
326#undef CONFIG_EEPRO100
327#undef CONFIG_TULIP
328#define CONFIG_RTL8139
329
330#ifdef CONFIG_RTL8139
331/* This macro is used by RTL8139 but not defined in PPC architecture */
332#define KSEG1ADDR(x) (x)
333#define _IO_BASE 0x00000000
334#endif
335
336#ifndef CONFIG_PCI_PNP
337 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
338 #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE
339 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
340#endif
341
342#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
343#define CONFIG_DOS_PARTITION
344#define CONFIG_SCSI_AHCI
345
346#ifdef CONFIG_SCSI_AHCI
347#define CONFIG_SATA_ULI5288
348#define CFG_SCSI_MAX_SCSI_ID 4
349#define CFG_SCSI_MAX_LUN 1
Ed Swarthout52b98522007-07-27 01:50:51 -0500350#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500351#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
352#endif /* SCSCI */
353
354#endif /* CONFIG_PCI */
355
356
357#if defined(CONFIG_TSEC_ENET)
358
359#ifndef CONFIG_NET_MULTI
Ed Swarthout52b98522007-07-27 01:50:51 -0500360#define CONFIG_NET_MULTI 1
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500361#endif
362
363#define CONFIG_MII 1 /* MII PHY management */
364#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
Kim Phillips177e58f2007-05-16 16:52:19 -0500365#define CONFIG_TSEC1 1
366#define CONFIG_TSEC1_NAME "eTSEC1"
367#define CONFIG_TSEC3 1
368#define CONFIG_TSEC3_NAME "eTSEC3"
Ed Swarthout52b98522007-07-27 01:50:51 -0500369
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500370#define TSEC1_PHY_ADDR 0
371#define TSEC3_PHY_ADDR 1
372
Andy Fleming09b88df2007-08-15 20:03:25 -0500373#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
374#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
375
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500376#define TSEC1_PHYIDX 0
377#define TSEC3_PHYIDX 0
378
379#define CONFIG_ETHPRIME "eTSEC1"
380
381#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500382#endif /* CONFIG_TSEC_ENET */
383
384/*
385 * Environment
386 */
387#define CFG_ENV_IS_IN_FLASH 1
388#if CFG_MONITOR_BASE > 0xfff80000
389#define CFG_ENV_ADDR 0xfff80000
390#else
Kumar Gala559e5312008-07-14 14:07:03 -0500391#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500392#endif
393#define CFG_ENV_SIZE 0x2000
394#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
395
396#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
397#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
398
Jon Loeligere63319f2007-06-13 13:22:08 -0500399/*
Jon Loeligered26c742007-07-10 09:10:49 -0500400 * BOOTP options
401 */
402#define CONFIG_BOOTP_BOOTFILESIZE
403#define CONFIG_BOOTP_BOOTPATH
404#define CONFIG_BOOTP_GATEWAY
405#define CONFIG_BOOTP_HOSTNAME
406
407
408/*
Jon Loeligere63319f2007-06-13 13:22:08 -0500409 * Command line configuration.
410 */
411#include <config_cmd_default.h>
412
413#define CONFIG_CMD_PING
414#define CONFIG_CMD_I2C
415#define CONFIG_CMD_MII
Kumar Gala260fac32007-12-07 12:04:30 -0600416#define CONFIG_CMD_ELF
Jon Loeligere63319f2007-06-13 13:22:08 -0500417
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500418#if defined(CONFIG_PCI)
Jon Loeligere63319f2007-06-13 13:22:08 -0500419 #define CONFIG_CMD_PCI
420 #define CONFIG_CMD_BEDBUG
421 #define CONFIG_CMD_NET
Ed Swarthout52b98522007-07-27 01:50:51 -0500422 #define CONFIG_CMD_SCSI
423 #define CONFIG_CMD_EXT2
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500424#endif
Jon Loeligere63319f2007-06-13 13:22:08 -0500425
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500426
427#undef CONFIG_WATCHDOG /* watchdog disabled */
428
429/*
430 * Miscellaneous configurable options
431 */
432#define CFG_LONGHELP /* undef to save memory */
Kumar Gala937176b2007-11-27 22:42:34 -0600433#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500434#define CFG_LOAD_ADDR 0x2000000 /* default load address */
435#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere63319f2007-06-13 13:22:08 -0500436#if defined(CONFIG_CMD_KGDB)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500437#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
438#else
439#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
440#endif
441#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
442#define CFG_MAXARGS 16 /* max number of command args */
443#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
444#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
445
446/*
447 * For booting Linux, the board info and command line data
448 * have to be in the first 8 MB of memory, since this is
449 * the maximum mapped by the Linux kernel during initialization.
450 */
Ed Swarthout52b98522007-07-27 01:50:51 -0500451#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500452
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500453/*
454 * Internal Definitions
455 *
456 * Boot Flags
457 */
458#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
459#define BOOTFLAG_WARM 0x02 /* Software reboot */
460
Jon Loeligere63319f2007-06-13 13:22:08 -0500461#if defined(CONFIG_CMD_KGDB)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500462#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
463#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
464#endif
465
466/*
467 * Environment Configuration
468 */
469
470/* The mac addresses for all ethernet interface */
471#if defined(CONFIG_TSEC_ENET)
Kumar Gala0eb61912007-08-16 11:01:21 -0500472#define CONFIG_HAS_ETH0
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500473#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
474#define CONFIG_HAS_ETH1
475#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500476#endif
477
478#define CONFIG_IPADDR 192.168.1.251
479
480#define CONFIG_HOSTNAME 8544ds_unknown
481#define CONFIG_ROOTPATH /nfs/mpc85xx
Ed Swarthout52b98522007-07-27 01:50:51 -0500482#define CONFIG_BOOTFILE 8544ds/uImage.uboot
483#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500484
Kumar Gala937176b2007-11-27 22:42:34 -0600485#define CONFIG_SERVERIP 192.168.1.1
486#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500487#define CONFIG_NETMASK 255.255.0.0
488
489#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
490
491#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Ed Swarthout52b98522007-07-27 01:50:51 -0500492#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500493
494#define CONFIG_BAUDRATE 115200
495
Ed Swarthout52b98522007-07-27 01:50:51 -0500496#define CONFIG_EXTRA_ENV_SETTINGS \
497 "netdev=eth0\0" \
498 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
499 "tftpflash=tftpboot $loadaddr $uboot; " \
500 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
501 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
502 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
503 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
504 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500505 "consoledev=ttyS0\0" \
506 "ramdiskaddr=2000000\0" \
Ed Swarthout52b98522007-07-27 01:50:51 -0500507 "ramdiskfile=8544ds/ramdisk.uboot\0" \
Kumar Gala937176b2007-11-27 22:42:34 -0600508 "fdtaddr=c00000\0" \
509 "fdtfile=8544ds/mpc8544ds.dtb\0" \
510 "bdev=sda3\0"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500511
512#define CONFIG_NFSBOOTCOMMAND \
513 "setenv bootargs root=/dev/nfs rw " \
514 "nfsroot=$serverip:$rootpath " \
515 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
516 "console=$consoledev,$baudrate $othbootargs;" \
517 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600518 "tftp $fdtaddr $fdtfile;" \
519 "bootm $loadaddr - $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500520
Ed Swarthout52b98522007-07-27 01:50:51 -0500521#define CONFIG_RAMBOOTCOMMAND \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500522 "setenv bootargs root=/dev/ram rw " \
523 "console=$consoledev,$baudrate $othbootargs;" \
524 "tftp $ramdiskaddr $ramdiskfile;" \
525 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600526 "tftp $fdtaddr $fdtfile;" \
527 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500528
Ed Swarthout52b98522007-07-27 01:50:51 -0500529#define CONFIG_BOOTCOMMAND \
530 "setenv bootargs root=/dev/$bdev rw " \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500531 "console=$consoledev,$baudrate $othbootargs;" \
532 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600533 "tftp $fdtaddr $fdtfile;" \
534 "bootm $loadaddr - $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500535
536#endif /* __CONFIG_H */