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git01.mediatek.com / filogic / uboot / 7262f3891b225e88232088a40083ac08773a5f4a / . / arch / arm / dts / am335x-rut.dts
blob: a5716a929f6683933f2cde0c3879a34da84748e4 [file] [log] [blame]
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]1/*
2 * Copyright (C) 2014 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
4 *
5 * Based on:
6 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12/dts-v1/;
13
14#include "am33xx.dtsi"
15#include <dt-bindings/input/input.h>
16
17/ {
18 model = "RUT";
19 compatible = "ti,am335x-evm", "ti,am33xx";
20
21 buzzer {
22 compatible = "pwm-beeper";
23 pwms = <&ecap0 0 16000 0>;
24 };
25
26 chosen {
27 stdout-path = &uart0;
28 tick-timer = &timer2;
29 };
30
31 cpus {
32 cpu@0 {
33 cpu0-supply = <&dcdc2_reg>;
34 };
35 };
36
37 gpio_keys: powerfail-keys {
38 compatible = "gpio-keys";
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]39 autorepeat;
40
41 pwr-fail0 {
42 label = "power-fail";
43 linux,code = <KEY_POWER>;
44 gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
45 gpio-key,wakeup;
46 };
47
48 pwr-fail1 {
49 label = "power-fail-redundant";
50 linux,code = <KEY_POWER>;
51 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
52 gpio-key,wakeup;
53 };
54 };
55
56 leds {
57 compatible = "gpio-leds";
58
59 led_green {
60 label = "rut:green:debug:run_mode";
61 gpios = <&gpio3 20 1>;
62 /* activelow = 1, default trigger heartbeat */
63 };
64 led_yellow {
65 label = "rut:debug:yellow:osc_ch1";
66 gpios = <&gpio0 17 1>;
67 /* activelow = 1, default trigger mmc0 */
68 };
69 led_red {
70 label = "rut:debug:red:osc_ch2";
71 gpios = <&gpio0 16 1>;
72 /* activelow = 1, default trigger debug_osc_ch2 */
73 };
74 /* optional */
75 led_alive {
76 label = "rut:alive";
77 gpios = <&gpio0 15 1>;
78 linux,default-trigger = "heartbeat";
79 /* activelow = 1, default trigger heartbeat */
80 };
81
82 };
83
84 memory {
85 device_type = "memory";
86 reg = <0x80000000 0x10000000>; /* 256 MB */
87 };
88
89 panel {
90 compatible = "ti,tilcdc,panel";
91 pinctrl-names = "default";
92 pinctrl-0 = <&lcd_pins_s0>;
93 status = "okay";
94
95 /* FORMIKE_KWH043ST20_F01 */
96 panel-info {
97 ac-bias = <255>;
98 ac-bias-intrpt = <0>;
99 dma-burst-sz = <16>;
100 bpp = <16>;
101 fdd = <0x80>;
102 sync-edge = <0>;
103 sync-ctrl = <1>;
104 raster-order = <0>;
105 fifo-th = <0>;
106 tft-alt-mode = <0>;
107 invert-pxl-clk = <1>;
108 };
109
110 display-timings {
111 native-mode = <&timing1>;
112 timing1: 480x800p60 {
113 clock-frequency = <29925000>;
114 hactive = <480>;
115 vactive = <800>;
116 hfront-porch = <50>;
117 hback-porch = <50>;
118 hsync-len = <50>;
119 vback-porch = <50>;
120 vfront-porch = <50>;
121 vsync-len = <50>;
122 hsync-active = <1>;
123 vsync-active = <1>;
124 };
125 };
126 };
127
128 vmmc: fixedregulator3 {
129 compatible = "regulator-fixed";
130 regulator-name = "vmmc";
131 regulator-min-microvolt = <3300000>;
132 regulator-max-microvolt = <3300000>;
133 };
134
135 watchdog {
136 compatible = "linux,wdt-gpio";
137 gpios = <&gpio0 14 0>;
138 hw_algo = "level";
139 hw_margin_ms = <30000>;
140 };
141};
142
143&aes {
144 status = "okay";
145};
146
147&cppi41dma {
148 status = "okay";
149};
150
151&cpsw_emac0 {
152 phy_id = <&davinci_mdio>, <1>;
153 phy-mode = "rmii";
154};
155
156&cpsw_emac1 {
157 phy_id = <&davinci_mdio>, <0>;
158 phy-mode = "rmii";
159};
160
161&davinci_mdio {
162 pinctrl-names = "default", "sleep";
163 pinctrl-0 = <&davinci_mdio_default>;
164 pinctrl-1 = <&davinci_mdio_sleep>;
165 status = "okay";
166 gpios = <&gpio2 18 0>;
167
168 ethernet_phy: ethernet-phy@1 {
169 compatible = "ethernet-phy-id2000.5ce1";
170 reg = <1>;
171 natsemi,master_mode_fixup;
172 };
173};
174
175&elm {
176 status = "okay";
177};
178
179&epwmss0 {
180 status = "okay";
181
182 ecap0: ecap@48300100 {
183 status = "okay";
184 pinctrl-names = "default";
185 pinctrl-0 = <&ecap0_pins>;
186 };
187};
188
189&epwmss1 {
190 status = "okay";
Felix Brack7262f382018-12-05 14:53:42 +0100[diff] [blame^]191 pinctrl-names = "default";
192 pinctrl-0 = <&epwmss1_pins>;
Heiko Schocher107ef972016-06-13 15:16:01 +0200[diff] [blame]193};
194
195&gpmc {
196 pinctrl-names = "default";
197 pinctrl-0 = <&nandflash_pins>;
198 status = "okay";
199
200 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
201
202 nand@0,0 {
203 reg = <0 0 0>; /* CS0, offset 0 */
204 nand-bus-width = <8>;
205 ti,nand-ecc-opt = "bch8";
206 gpmc,device-nand = "true";
207 gpmc,device-width = <1>;
208 gpmc,sync-clk-ps = <0>;
209 gpmc,cs-on-ns = <0>;
210 gpmc,cs-rd-off-ns = <57>;
211 gpmc,cs-wr-off-ns = <57>;
212 gpmc,adv-on-ns = <0>;
213 gpmc,adv-rd-off-ns = <57>;
214 gpmc,adv-wr-off-ns = <57>;
215 gpmc,we-on-ns = <0>;
216 gpmc,we-off-ns = <48>;
217 gpmc,oe-on-ns = <0>;
218 gpmc,oe-off-ns = <57>;
219 gpmc,access-ns = <38>;
220 gpmc,rd-cycle-ns = <67>;
221 gpmc,wr-cycle-ns = <67>;
222 gpmc,wait-on-read = "true";
223 gpmc,wait-on-write = "true";
224 gpmc,bus-turnaround-ns = <0>;
225 gpmc,cycle2cycle-delay-ns = <0>;
226 gpmc,clk-activation-ns = <0>;
227 gpmc,wait-monitoring-ns = <0>;
228 gpmc,wr-access-ns = <96>;
229 gpmc,wr-data-mux-bus-ns = <0>;
230
231 #address-cells = <1>;
232 #size-cells = <1>;
233 elm_id = <&elm>;
234 };
235};
236
237&i2c0 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&i2c0_pins>;
240 clock-frequency = <400000>;
241 status = "okay";
242
243 eeprom: eeprom@50 {
244 compatible = "atmel,24c128";
245 reg = <0x50>;
246 pagesize = <32>;
247 };
248
249 tps: tps@24 {
250 reg = <0x24>;
251 };
252};
253
254&i2c1 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&i2c1_pins>;
257 clock-frequency = <100000>;
258 status = "okay";
259
260 atmel: atmel_mxt_ts@4a {
261 compatible = "atmel,maxtouch";
262 reg = <0x4a>;
263 interrupt-parent = <&gpio1>;
264 interrupts = <28 8>;
265 gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
266 };
267
268 temp@48 {
269 compatible = "st,ds75";
270 reg = <0x4c>;
271 };
272};
273
274&lcdc {
275 status = "okay";
276};
277
278&mac {
279 pinctrl-names = "default", "sleep";
280 pinctrl-0 = <&cpsw_default>;
281 pinctrl-1 = <&cpsw_sleep>;
282 status = "okay";
283};
284
285&mmc1 {
286 vmmc-supply = <&vmmc>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&mmc1_pins>;
289 status = "okay";
290};
291
292&phy_sel {
293 rmii-clock-ext;
294};
295
296&sham {
297 status = "okay";
298};
299
300&spi0 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&spi0_pins>;
303 status = "okay";
304 spi-flash@0 {
305 #address-cells = <1>;
306 #size-cells = <1>;
307 compatible = "mx25l25635e";
308 reg = <0>; /* Chip select 0 */
309 spi-max-frequency = <24000000>;
310
311 partition@0 {
312 label = "dummy";
313 reg = <0x0000000 0x8000>;
314 };
315 };
316};
317
318&spi1 {
319 pinctrl-names = "default";
320 pinctrl-0 = <&spi1_pins>;
321 status = "okay";
322
323 lcd_init: lcd@0 {
324 compatible = "formike,kwh043st20";
325 reg = <0>;
326 reset-gpios = <&gpio3 19 0>;
327 spi-max-frequency = <1200000>;
328 spi-cpol;
329 spi-cpha;
330 power-on-delay = <10>;
331 reset-delay = <10>;
332 };
333};
334
335/include/ "tps65217.dtsi"
336
337&tps {
338 backlight0: backlight {
339 isel = <1>; /* 1 - ISET1, 2 ISET2 */
340 fdim = <1000>; /* TPS65217_BL_FDIM_100HZ */
341 default-brightness = <80>;
342 };
343
344 regulators {
345 dcdc1_reg: regulator@0 {
346 regulator-always-on;
347 };
348
349 dcdc2_reg: regulator@1 {
350 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
351 regulator-name = "vdd_mpu";
352 regulator-min-microvolt = <925000>;
353 regulator-max-microvolt = <1325000>;
354 regulator-boot-on;
355 regulator-always-on;
356 };
357
358 dcdc3_reg: regulator@2 {
359 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
360 regulator-name = "vdd_core";
361 regulator-min-microvolt = <925000>;
362 regulator-max-microvolt = <1150000>;
363 regulator-boot-on;
364 regulator-always-on;
365 };
366
367 ldo1_reg: regulator@3 {
368 regulator-always-on;
369 };
370
371 ldo2_reg: regulator@4 {
372 regulator-always-on;
373 };
374
375 ldo3_reg: regulator@5 {
376 regulator-always-on;
377 };
378
379 ldo4_reg: regulator@6 {
380 regulator-always-on;
381 };
382 };
383};
384
385&tscadc {
386 status = "okay";
387 adc {
388 ti,adc-channels = <4 5 6 7>;
389 };
390};
391
392&uart0 {
393 pinctrl-names = "default";
394 pinctrl-0 = <&uart0_pins>;
395
396 status = "okay";
397};
398
399&usb {
400 status = "okay";
401};
402
403&usb_ctrl_mod {
404 status = "okay";
405};
406
407&usb0 {
408 dr_mode = "device";
409 status = "okay";
410};
411
412&usb0_phy {
413 status = "okay";
414};
415
416&am33xx_pinmux {
417 pinctrl-names = "default";
418 pinctrl-0 = <&clkout2_pin &gpio_pin>;
419
420 clkout2_pin: pinmux_clkout2_pin {
421 pinctrl-single,pins = <
422 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
423 >;
424 };
425
426 cpsw_default: cpsw_default {
427 pinctrl-single,pins = <
428 /* Slave 1 */
429 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
430 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.mii1_rxerr */
431 0x114 (MUX_MODE1) /* mii1_txen.mii1_txen */
432 0x124 (MUX_MODE1) /* mii1_txd1.mii1_txd1 */
433 0x128 (MUX_MODE1) /* mii1_txd0.mii1_txd0 */
434 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.mii1_rxd1 */
435 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.mii1_rxd0 */
436 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
437 >;
438 };
439
440 cpsw_sleep: cpsw_sleep {
441 pinctrl-single,pins = <
442 /* Slave 1 reset value */
443 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
444 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
445 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
446 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
447 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
448 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
449 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
450 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
451 >;
452 };
453
454 davinci_mdio_default: davinci_mdio_default {
455 pinctrl-single,pins = <
456 /* MDIO */
457 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
458 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
459 >;
460 };
461
462 davinci_mdio_sleep: davinci_mdio_sleep {
463 pinctrl-single,pins = <
464 /* MDIO reset value */
465 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
466 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
467 >;
468 };
469
470 ecap0_pins: ecap_pins {
471 pinctrl-single,pins = <
472 0x164 (MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 buzzer frequency: ecap.0 */
473 >;
474 };
475
476 epwmss1_pins: epwmss_pins {
477 pinctrl-single,pins = <
478 0x48 (PIN_INPUT | MUX_MODE7) /* gpmc_a2.gpio1_18 buzzer frequency: ehrpwm1A high-Z due to connected to ecap0 by R0469 */
479 0x4c (MUX_MODE6) /* gpmc_a3.ehrpwm1B buzzer volume pwm */
480 >;
481 };
482
483 gpio_pin: gpio_pin {
484 pinctrl-single,pins = <
485 0x6c (PIN_INPUT | MUX_MODE7) /* gpmc_a11.gpio1_27 PWR_FAIL_GPIO_SPARE */
486 0x78 (PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) /* gpmc_be1n.gpio1_28 TOUCH_CHANGE_N */
487 0x88 (PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7) /* gpmc_csn3.gpio2_0 RUT_GPIO0_GPIO */
488 0x118 (PIN_INPUT | MUX_MODE7) /* gmii1_rxdv.gpio3_4 PWR_FAIL_GPIO */
489 0x11c (MUX_MODE7) /* mii1_txd3.gpio0_16 DEBUG_OSC_CH2_GPIO */
490 0x120 (MUX_MODE7) /* mii1_txd2.gpio0_17 DEBUG_OSC_CH1_GPIO */
491 0x134 (MUX_MODE7) /* gmii1_rxd3.gpio2_18 PHY_RSTn_GPIO */
492 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gmii1_rxd2.gpio2_19 PHY_INT_GPIO */
493 0x180 (MUX_MODE7) /* uart1_rxd.gpio0_14 WATCHDOG_TRIGGER_GPIO */
494 0x184 (MUX_MODE7) /* uart1_txd.gpio0_15 ALIVE_LED_N_GPIO */
495 0x1a0 (MUX_MODE7) /* mcasp0_aclkr.gpio3_18 MAXTOUCH_RESET_GPIO */
496 0x1a4 (MUX_MODE7) /* mcasp0_fsr.gpio3_19 DISPLAY_RESET_GPIO */
497 0x1a8 (MUX_MODE7) /* mcasp0_axr1.gpio3_20 DEBUG_RUN_MODE_GPIO */
498 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 NORFLASH_WP_GPIO */
499 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
500 >;
501 };
502
503 i2c0_pins: pinmux_i2c0_pins {
504 pinctrl-single,pins = <
505 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
506 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
507 >;
508 };
509
510 i2c1_pins: pinmux_i2c1_pins {
511 pinctrl-single,pins = <
512 0x168 (PIN_INPUT | MUX_MODE3) /* uart0_ctsn.i2c1_sda */
513 0x16c (PIN_INPUT | MUX_MODE3) /* uart0.rtsn.i2c1_scl */
514 >;
515 };
516
517 lcd_pins_s0: lcd_pins_s0 {
518 pinctrl-single,pins = <
519 0x20 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
520 0x24 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
521 0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
522 0x2c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
523 0x30 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
524 0x34 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
525 0x38 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
526 0x3c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
527 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
528 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
529 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
530 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
531 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
532 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
533 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
534 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
535 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
536 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
537 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
538 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
539 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
540 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
541 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
542 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
543 0xe0 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */
544 0xe4 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */
545 0xe8 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */
546 0xec (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
547 >;
548 };
549
550 mmc1_pins: mmc1_pins {
551 pinctrl-single,pins = <
552 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
553 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
554 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
555 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
556 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
557 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
558 >;
559 };
560
561 nandflash_pins: pinmux_nandflash_pins {
562 pinctrl-single,pins = <
563 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
564 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
565 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
566 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
567 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
568 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
569 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
570 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
571 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
572 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
573 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
574 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
575 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
576 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
577 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
578 >;
579 };
580
581 spi0_pins: pinmux_spi0_pins {
582 pinctrl-single,pins = <
583 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_sclk.spi0_sclk */
584 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
585 0x158 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d1.spi0_d1 */
586 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_CS0.spi0_CS0 */
587 >;
588 };
589
590 spi1_pins: pinmux_spi1_pins {
591 pinctrl-single,pins = <
592 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
593 0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
594 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
595 0x19c (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
596 >;
597 };
598
599 uart0_pins: pinmux_uart0_pins {
600 pinctrl-single,pins = <
601 0x170 (PIN_INPUT | MUX_MODE0) /* uart0_rxd.uart0_rxd */
602 0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
603 >;
604 };
605};