dts/upstream/Bindings/mmc/sdhci-am654.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI AM654 MMC Controller

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

allOf:
  - $ref: sdhci-common.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - ti,am62-sdhci
          - ti,am64-sdhci-4bit
          - ti,am64-sdhci-8bit
          - ti,am654-sdhci-5.1
          - ti,j721e-sdhci-4bit
          - ti,j721e-sdhci-8bit
      - items:
          - const: ti,j7200-sdhci-8bit
          - const: ti,j721e-sdhci-8bit
      - items:
          - const: ti,j7200-sdhci-4bit
          - const: ti,j721e-sdhci-4bit

  reg:
    maxItems: 2

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2
    description: Handles to input clocks

  clock-names:
    minItems: 1
    items:
      - const: clk_ahb
      - const: clk_xin

  dma-coherent:
    type: boolean

  # PHY output tap delays:
  # Used to delay the data valid window and align it to the sampling clock.
  # Binding needs to be provided for each supported speed mode otherwise the
  # corresponding mode will be disabled.

  ti,otap-del-sel-legacy:
    description: Output tap delay for SD/MMC legacy timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-mmc-hs:
    description: Output tap delay for MMC high speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sd-hs:
    description: Output tap delay for SD high speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sdr12:
    description: Output tap delay for SD UHS SDR12 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sdr25:
    description: Output tap delay for SD UHS SDR25 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sdr50:
    description: Output tap delay for SD UHS SDR50 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sdr104:
    description: Output tap delay for SD UHS SDR104 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-ddr50:
    description: Output tap delay for SD UHS DDR50 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-ddr52:
    description: Output tap delay for eMMC DDR52 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-hs200:
    description: Output tap delay for eMMC HS200 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-hs400:
    description: Output tap delay for eMMC HS400 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  # PHY input tap delays:
  # Used to delay the data valid window and align it to the sampling clock for
  # modes that don't support tuning

  ti,itap-del-sel-legacy:
    description: Input tap delay for SD/MMC legacy timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-mmc-hs:
    description: Input tap delay for MMC high speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-sd-hs:
    description: Input tap delay for SD high speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-sdr12:
    description: Input tap delay for SD UHS SDR12 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-sdr25:
    description: Input tap delay for SD UHS SDR25 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-ddr50:
    description: Input tap delay for MMC DDR50 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-ddr52:
    description: Input tap delay for MMC DDR52 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,trm-icp:
    description: DLL trim select
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,driver-strength-ohm:
    description: DLL drive strength in ohms
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 33
      - 40
      - 50
      - 66
      - 100

  ti,strobe-sel:
    description: strobe select delay for HS400 speed mode.
    $ref: /schemas/types.yaml#/definitions/uint32

  ti,clkbuf-sel:
    description: Clock Delay Buffer Select
    $ref: /schemas/types.yaml#/definitions/uint32

  ti,fails-without-test-cd:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      When present, indicates that the CD line is not connected
      and the controller is required to be forced into Test mode
      to set the TESTCD bit.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - ti,otap-del-sel-legacy

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        mmc0: mmc@4f80000 {
            compatible = "ti,am654-sdhci-5.1";
            reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
            power-domains = <&k3_pds 47>;
            clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
            clock-names = "clk_ahb", "clk_xin";
            interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
            sdhci-caps-mask = <0x80000007 0x0>;
            mmc-ddr-1_8v;
            ti,otap-del-sel-legacy = <0x0>;
            ti,otap-del-sel-mmc-hs = <0x0>;
            ti,otap-del-sel-ddr52 = <0x5>;
            ti,otap-del-sel-hs200 = <0x5>;
            ti,otap-del-sel-hs400 = <0x0>;
            ti,itap-del-sel-legacy = <0x10>;
            ti,itap-del-sel-mmc-hs = <0xa>;
            ti,itap-del-sel-ddr52 = <0x3>;
            ti,trm-icp = <0x8>;
        };
    };