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git01.mediatek.com / filogic / uboot / 7231ce3cbdb4dd9aa4478a791d3931577efcb7e9 / . / dts / upstream / Bindings / memory-controllers / nvidia,tegra124-emc.yaml
blob: f5f03bf364137cd50aba871cb1bb4bd4ffc7021d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra124 SoC External Memory Controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13description: |
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
16
17properties:
18 compatible:
19 const: nvidia,tegra124-emc
20
21 reg:
22 maxItems: 1
23
24 clocks:
25 items:
26 - description: external memory clock
27
28 clock-names:
29 items:
30 - const: emc
31
32 "#interconnect-cells":
33 const: 0
34
35 nvidia,memory-controller:
36 $ref: /schemas/types.yaml#/definitions/phandle
37 description:
38 phandle of the memory controller node
39
40 power-domains:
41 maxItems: 1
42 description:
43 Phandle of the SoC "core" power domain.
44
45 operating-points-v2:
46 description:
47 Should contain freqs and voltages and opp-supported-hw property, which
48 is a bitfield indicating SoC speedo ID mask.
49
50patternProperties:
51 "^emc-timings-[0-9]+$":
52 type: object
53 additionalProperties: false
54 properties:
55 nvidia,ram-code:
56 $ref: /schemas/types.yaml#/definitions/uint32
57 description:
58 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
59 this timing set is used for
60
61 patternProperties:
62 "^timing-[0-9]+$":
63 type: object
64 properties:
65 clock-frequency:
66 description:
67 external memory clock rate in Hz
68 minimum: 1000000
69 maximum: 1000000000
70
71 nvidia,emc-auto-cal-config:
72 $ref: /schemas/types.yaml#/definitions/uint32
73 description:
74 value of the EMC_AUTO_CAL_CONFIG register for this set of
75 timings
76
77 nvidia,emc-auto-cal-config2:
78 $ref: /schemas/types.yaml#/definitions/uint32
79 description:
80 value of the EMC_AUTO_CAL_CONFIG2 register for this set of
81 timings
82
83 nvidia,emc-auto-cal-config3:
84 $ref: /schemas/types.yaml#/definitions/uint32
85 description:
86 value of the EMC_AUTO_CAL_CONFIG3 register for this set of
87 timings
88
89 nvidia,emc-auto-cal-interval:
90 description:
91 pad calibration interval in microseconds
92 $ref: /schemas/types.yaml#/definitions/uint32
93 minimum: 0
94 maximum: 2097151
95
96 nvidia,emc-bgbias-ctl0:
97 $ref: /schemas/types.yaml#/definitions/uint32
98 description:
99 value of the EMC_BGBIAS_CTL0 register for this set of timings
100
101 nvidia,emc-cfg:
102 $ref: /schemas/types.yaml#/definitions/uint32
103 description:
104 value of the EMC_CFG register for this set of timings
105
106 nvidia,emc-cfg-2:
107 $ref: /schemas/types.yaml#/definitions/uint32
108 description:
109 value of the EMC_CFG_2 register for this set of timings
110
111 nvidia,emc-ctt-term-ctrl:
112 $ref: /schemas/types.yaml#/definitions/uint32
113 description:
114 value of the EMC_CTT_TERM_CTRL register for this set of timings
115
116 nvidia,emc-mode-1:
117 $ref: /schemas/types.yaml#/definitions/uint32
118 description:
119 value of the EMC_MRW register for this set of timings
120
121 nvidia,emc-mode-2:
122 $ref: /schemas/types.yaml#/definitions/uint32
123 description:
124 value of the EMC_MRW2 register for this set of timings
125
126 nvidia,emc-mode-4:
127 $ref: /schemas/types.yaml#/definitions/uint32
128 description:
129 value of the EMC_MRW4 register for this set of timings
130
131 nvidia,emc-mode-reset:
132 $ref: /schemas/types.yaml#/definitions/uint32
133 description:
134 reset value of the EMC_MRS register for this set of timings
135
136 nvidia,emc-mrs-wait-cnt:
137 $ref: /schemas/types.yaml#/definitions/uint32
138 description:
139 value of the EMR_MRS_WAIT_CNT register for this set of timings
140
141 nvidia,emc-sel-dpd-ctrl:
142 $ref: /schemas/types.yaml#/definitions/uint32
143 description:
144 value of the EMC_SEL_DPD_CTRL register for this set of timings
145
146 nvidia,emc-xm2dqspadctrl2:
147 $ref: /schemas/types.yaml#/definitions/uint32
148 description:
149 value of the EMC_XM2DQSPADCTRL2 register for this set of timings
150
151 nvidia,emc-zcal-cnt-long:
152 description:
153 number of EMC clocks to wait before issuing any commands after
154 clock change
155 $ref: /schemas/types.yaml#/definitions/uint32
156 minimum: 0
157 maximum: 1023
158
159 nvidia,emc-zcal-interval:
160 $ref: /schemas/types.yaml#/definitions/uint32
161 description:
162 value of the EMC_ZCAL_INTERVAL register for this set of timings
163
164 nvidia,emc-configuration:
165 description:
166 EMC timing characterization data. These are the registers (see
167 section "15.6.2 EMC Registers" in the TRM) whose values need to
168 be specified, according to the board documentation.
169 $ref: /schemas/types.yaml#/definitions/uint32-array
170 items:
171 - description: EMC_RC
172 - description: EMC_RFC
173 - description: EMC_RFC_SLR
174 - description: EMC_RAS
175 - description: EMC_RP
176 - description: EMC_R2W
177 - description: EMC_W2R
178 - description: EMC_R2P
179 - description: EMC_W2P
180 - description: EMC_RD_RCD
181 - description: EMC_WR_RCD
182 - description: EMC_RRD
183 - description: EMC_REXT
184 - description: EMC_WEXT
185 - description: EMC_WDV
186 - description: EMC_WDV_MASK
187 - description: EMC_QUSE
188 - description: EMC_QUSE_WIDTH
189 - description: EMC_IBDLY
190 - description: EMC_EINPUT
191 - description: EMC_EINPUT_DURATION
192 - description: EMC_PUTERM_EXTRA
193 - description: EMC_PUTERM_WIDTH
194 - description: EMC_PUTERM_ADJ
195 - description: EMC_CDB_CNTL_1
196 - description: EMC_CDB_CNTL_2
197 - description: EMC_CDB_CNTL_3
198 - description: EMC_QRST
199 - description: EMC_QSAFE
200 - description: EMC_RDV
201 - description: EMC_RDV_MASK
202 - description: EMC_REFRESH
203 - description: EMC_BURST_REFRESH_NUM
204 - description: EMC_PRE_REFRESH_REQ_CNT
205 - description: EMC_PDEX2WR
206 - description: EMC_PDEX2RD
207 - description: EMC_PCHG2PDEN
208 - description: EMC_ACT2PDEN
209 - description: EMC_AR2PDEN
210 - description: EMC_RW2PDEN
211 - description: EMC_TXSR
212 - description: EMC_TXSRDLL
213 - description: EMC_TCKE
214 - description: EMC_TCKESR
215 - description: EMC_TPD
216 - description: EMC_TFAW
217 - description: EMC_TRPAB
218 - description: EMC_TCLKSTABLE
219 - description: EMC_TCLKSTOP
220 - description: EMC_TREFBW
221 - description: EMC_FBIO_CFG6
222 - description: EMC_ODT_WRITE
223 - description: EMC_ODT_READ
224 - description: EMC_FBIO_CFG5
225 - description: EMC_CFG_DIG_DLL
226 - description: EMC_CFG_DIG_DLL_PERIOD
227 - description: EMC_DLL_XFORM_DQS0
228 - description: EMC_DLL_XFORM_DQS1
229 - description: EMC_DLL_XFORM_DQS2
230 - description: EMC_DLL_XFORM_DQS3
231 - description: EMC_DLL_XFORM_DQS4
232 - description: EMC_DLL_XFORM_DQS5
233 - description: EMC_DLL_XFORM_DQS6
234 - description: EMC_DLL_XFORM_DQS7
235 - description: EMC_DLL_XFORM_DQS8
236 - description: EMC_DLL_XFORM_DQS9
237 - description: EMC_DLL_XFORM_DQS10
238 - description: EMC_DLL_XFORM_DQS11
239 - description: EMC_DLL_XFORM_DQS12
240 - description: EMC_DLL_XFORM_DQS13
241 - description: EMC_DLL_XFORM_DQS14
242 - description: EMC_DLL_XFORM_DQS15
243 - description: EMC_DLL_XFORM_QUSE0
244 - description: EMC_DLL_XFORM_QUSE1
245 - description: EMC_DLL_XFORM_QUSE2
246 - description: EMC_DLL_XFORM_QUSE3
247 - description: EMC_DLL_XFORM_QUSE4
248 - description: EMC_DLL_XFORM_QUSE5
249 - description: EMC_DLL_XFORM_QUSE6
250 - description: EMC_DLL_XFORM_QUSE7
251 - description: EMC_DLL_XFORM_ADDR0
252 - description: EMC_DLL_XFORM_ADDR1
253 - description: EMC_DLL_XFORM_ADDR2
254 - description: EMC_DLL_XFORM_ADDR3
255 - description: EMC_DLL_XFORM_ADDR4
256 - description: EMC_DLL_XFORM_ADDR5
257 - description: EMC_DLL_XFORM_QUSE8
258 - description: EMC_DLL_XFORM_QUSE9
259 - description: EMC_DLL_XFORM_QUSE10
260 - description: EMC_DLL_XFORM_QUSE11
261 - description: EMC_DLL_XFORM_QUSE12
262 - description: EMC_DLL_XFORM_QUSE13
263 - description: EMC_DLL_XFORM_QUSE14
264 - description: EMC_DLL_XFORM_QUSE15
265 - description: EMC_DLI_TRIM_TXDQS0
266 - description: EMC_DLI_TRIM_TXDQS1
267 - description: EMC_DLI_TRIM_TXDQS2
268 - description: EMC_DLI_TRIM_TXDQS3
269 - description: EMC_DLI_TRIM_TXDQS4
270 - description: EMC_DLI_TRIM_TXDQS5
271 - description: EMC_DLI_TRIM_TXDQS6
272 - description: EMC_DLI_TRIM_TXDQS7
273 - description: EMC_DLI_TRIM_TXDQS8
274 - description: EMC_DLI_TRIM_TXDQS9
275 - description: EMC_DLI_TRIM_TXDQS10
276 - description: EMC_DLI_TRIM_TXDQS11
277 - description: EMC_DLI_TRIM_TXDQS12
278 - description: EMC_DLI_TRIM_TXDQS13
279 - description: EMC_DLI_TRIM_TXDQS14
280 - description: EMC_DLI_TRIM_TXDQS15
281 - description: EMC_DLL_XFORM_DQ0
282 - description: EMC_DLL_XFORM_DQ1
283 - description: EMC_DLL_XFORM_DQ2
284 - description: EMC_DLL_XFORM_DQ3
285 - description: EMC_DLL_XFORM_DQ4
286 - description: EMC_DLL_XFORM_DQ5
287 - description: EMC_DLL_XFORM_DQ6
288 - description: EMC_DLL_XFORM_DQ7
289 - description: EMC_XM2CMDPADCTRL
290 - description: EMC_XM2CMDPADCTRL4
291 - description: EMC_XM2CMDPADCTRL5
292 - description: EMC_XM2DQPADCTRL2
293 - description: EMC_XM2DQPADCTRL3
294 - description: EMC_XM2CLKPADCTRL
295 - description: EMC_XM2CLKPADCTRL2
296 - description: EMC_XM2COMPPADCTRL
297 - description: EMC_XM2VTTGENPADCTRL
298 - description: EMC_XM2VTTGENPADCTRL2
299 - description: EMC_XM2VTTGENPADCTRL3
300 - description: EMC_XM2DQSPADCTRL3
301 - description: EMC_XM2DQSPADCTRL4
302 - description: EMC_XM2DQSPADCTRL5
303 - description: EMC_XM2DQSPADCTRL6
304 - description: EMC_DSR_VTTGEN_DRV
305 - description: EMC_TXDSRVTTGEN
306 - description: EMC_FBIO_SPARE
307 - description: EMC_ZCAL_WAIT_CNT
308 - description: EMC_MRS_WAIT_CNT2
309 - description: EMC_CTT
310 - description: EMC_CTT_DURATION
311 - description: EMC_CFG_PIPE
312 - description: EMC_DYN_SELF_REF_CONTROL
313 - description: EMC_QPOP
314
315 required:
316 - clock-frequency
317 - nvidia,emc-auto-cal-config
318 - nvidia,emc-auto-cal-config2
319 - nvidia,emc-auto-cal-config3
320 - nvidia,emc-auto-cal-interval
321 - nvidia,emc-bgbias-ctl0
322 - nvidia,emc-cfg
323 - nvidia,emc-cfg-2
324 - nvidia,emc-ctt-term-ctrl
325 - nvidia,emc-mode-1
326 - nvidia,emc-mode-2
327 - nvidia,emc-mode-4
328 - nvidia,emc-mode-reset
329 - nvidia,emc-mrs-wait-cnt
330 - nvidia,emc-sel-dpd-ctrl
331 - nvidia,emc-xm2dqspadctrl2
332 - nvidia,emc-zcal-cnt-long
333 - nvidia,emc-zcal-interval
334 - nvidia,emc-configuration
335
336 additionalProperties: false
337
338required:
339 - compatible
340 - reg
341 - clocks
342 - clock-names
343 - nvidia,memory-controller
344 - "#interconnect-cells"
345 - operating-points-v2
346
347additionalProperties: false
348
349examples:
350 - |
351 #include <dt-bindings/clock/tegra124-car.h>
352 #include <dt-bindings/interrupt-controller/arm-gic.h>
353
354 mc: memory-controller@70019000 {
355 compatible = "nvidia,tegra124-mc";
356 reg = <0x70019000 0x1000>;
357 clocks = <&tegra_car TEGRA124_CLK_MC>;
358 clock-names = "mc";
359
360 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
361
362 #iommu-cells = <1>;
363 #reset-cells = <1>;
364 #interconnect-cells = <1>;
365 };
366
367 external-memory-controller@7001b000 {
368 compatible = "nvidia,tegra124-emc";
369 reg = <0x7001b000 0x1000>;
370 clocks = <&car TEGRA124_CLK_EMC>;
371 clock-names = "emc";
372
373 nvidia,memory-controller = <&mc>;
374 operating-points-v2 = <&dvfs_opp_table>;
375 power-domains = <&domain>;
376
377 #interconnect-cells = <0>;
378
379 emc-timings-0 {
380 nvidia,ram-code = <3>;
381
382 timing-0 {
383 clock-frequency = <12750000>;
384
385 nvidia,emc-auto-cal-config = <0xa1430000>;
386 nvidia,emc-auto-cal-config2 = <0x00000000>;
387 nvidia,emc-auto-cal-config3 = <0x00000000>;
388 nvidia,emc-auto-cal-interval = <0x001fffff>;
389 nvidia,emc-bgbias-ctl0 = <0x00000008>;
390 nvidia,emc-cfg = <0x73240000>;
391 nvidia,emc-cfg-2 = <0x000008c5>;
392 nvidia,emc-ctt-term-ctrl = <0x00000802>;
393 nvidia,emc-mode-1 = <0x80100003>;
394 nvidia,emc-mode-2 = <0x80200008>;
395 nvidia,emc-mode-4 = <0x00000000>;
396 nvidia,emc-mode-reset = <0x80001221>;
397 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
398 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
399 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
400 nvidia,emc-zcal-cnt-long = <0x00000042>;
401 nvidia,emc-zcal-interval = <0x00000000>;
402
403 nvidia,emc-configuration = <
404 0x00000000 /* EMC_RC */
405 0x00000003 /* EMC_RFC */
406 0x00000000 /* EMC_RFC_SLR */
407 0x00000000 /* EMC_RAS */
408 0x00000000 /* EMC_RP */
409 0x00000004 /* EMC_R2W */
410 0x0000000a /* EMC_W2R */
411 0x00000003 /* EMC_R2P */
412 0x0000000b /* EMC_W2P */
413 0x00000000 /* EMC_RD_RCD */
414 0x00000000 /* EMC_WR_RCD */
415 0x00000003 /* EMC_RRD */
416 0x00000003 /* EMC_REXT */
417 0x00000000 /* EMC_WEXT */
418 0x00000006 /* EMC_WDV */
419 0x00000006 /* EMC_WDV_MASK */
420 0x00000006 /* EMC_QUSE */
421 0x00000002 /* EMC_QUSE_WIDTH */
422 0x00000000 /* EMC_IBDLY */
423 0x00000005 /* EMC_EINPUT */
424 0x00000005 /* EMC_EINPUT_DURATION */
425 0x00010000 /* EMC_PUTERM_EXTRA */
426 0x00000003 /* EMC_PUTERM_WIDTH */
427 0x00000000 /* EMC_PUTERM_ADJ */
428 0x00000000 /* EMC_CDB_CNTL_1 */
429 0x00000000 /* EMC_CDB_CNTL_2 */
430 0x00000000 /* EMC_CDB_CNTL_3 */
431 0x00000004 /* EMC_QRST */
432 0x0000000c /* EMC_QSAFE */
433 0x0000000d /* EMC_RDV */
434 0x0000000f /* EMC_RDV_MASK */
435 0x00000060 /* EMC_REFRESH */
436 0x00000000 /* EMC_BURST_REFRESH_NUM */
437 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
438 0x00000002 /* EMC_PDEX2WR */
439 0x00000002 /* EMC_PDEX2RD */
440 0x00000001 /* EMC_PCHG2PDEN */
441 0x00000000 /* EMC_ACT2PDEN */
442 0x00000007 /* EMC_AR2PDEN */
443 0x0000000f /* EMC_RW2PDEN */
444 0x00000005 /* EMC_TXSR */
445 0x00000005 /* EMC_TXSRDLL */
446 0x00000004 /* EMC_TCKE */
447 0x00000005 /* EMC_TCKESR */
448 0x00000004 /* EMC_TPD */
449 0x00000000 /* EMC_TFAW */
450 0x00000000 /* EMC_TRPAB */
451 0x00000005 /* EMC_TCLKSTABLE */
452 0x00000005 /* EMC_TCLKSTOP */
453 0x00000064 /* EMC_TREFBW */
454 0x00000000 /* EMC_FBIO_CFG6 */
455 0x00000000 /* EMC_ODT_WRITE */
456 0x00000000 /* EMC_ODT_READ */
457 0x106aa298 /* EMC_FBIO_CFG5 */
458 0x002c00a0 /* EMC_CFG_DIG_DLL */
459 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
460 0x00064000 /* EMC_DLL_XFORM_DQS0 */
461 0x00064000 /* EMC_DLL_XFORM_DQS1 */
462 0x00064000 /* EMC_DLL_XFORM_DQS2 */
463 0x00064000 /* EMC_DLL_XFORM_DQS3 */
464 0x00064000 /* EMC_DLL_XFORM_DQS4 */
465 0x00064000 /* EMC_DLL_XFORM_DQS5 */
466 0x00064000 /* EMC_DLL_XFORM_DQS6 */
467 0x00064000 /* EMC_DLL_XFORM_DQS7 */
468 0x00064000 /* EMC_DLL_XFORM_DQS8 */
469 0x00064000 /* EMC_DLL_XFORM_DQS9 */
470 0x00064000 /* EMC_DLL_XFORM_DQS10 */
471 0x00064000 /* EMC_DLL_XFORM_DQS11 */
472 0x00064000 /* EMC_DLL_XFORM_DQS12 */
473 0x00064000 /* EMC_DLL_XFORM_DQS13 */
474 0x00064000 /* EMC_DLL_XFORM_DQS14 */
475 0x00064000 /* EMC_DLL_XFORM_DQS15 */
476 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
477 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
478 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
479 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
480 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
481 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
482 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
483 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
484 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
485 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
486 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
487 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
488 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
489 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
490 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
491 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
492 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
493 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
494 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
495 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
496 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
497 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
498 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
499 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
500 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
501 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
502 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
503 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
504 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
505 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
506 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
507 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
508 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
509 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
510 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
511 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
512 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
513 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
514 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
515 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
516 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
517 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
518 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
519 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
520 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
521 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
522 0x10000280 /* EMC_XM2CMDPADCTRL */
523 0x00000000 /* EMC_XM2CMDPADCTRL4 */
524 0x00111111 /* EMC_XM2CMDPADCTRL5 */
525 0x00000000 /* EMC_XM2DQPADCTRL2 */
526 0x00000000 /* EMC_XM2DQPADCTRL3 */
527 0x77ffc081 /* EMC_XM2CLKPADCTRL */
528 0x00000e0e /* EMC_XM2CLKPADCTRL2 */
529 0x81f1f108 /* EMC_XM2COMPPADCTRL */
530 0x07070004 /* EMC_XM2VTTGENPADCTRL */
531 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
532 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
533 0x51451400 /* EMC_XM2DQSPADCTRL3 */
534 0x00514514 /* EMC_XM2DQSPADCTRL4 */
535 0x00514514 /* EMC_XM2DQSPADCTRL5 */
536 0x51451400 /* EMC_XM2DQSPADCTRL6 */
537 0x0000003f /* EMC_DSR_VTTGEN_DRV */
538 0x00000007 /* EMC_TXDSRVTTGEN */
539 0x00000000 /* EMC_FBIO_SPARE */
540 0x00000042 /* EMC_ZCAL_WAIT_CNT */
541 0x000e000e /* EMC_MRS_WAIT_CNT2 */
542 0x00000000 /* EMC_CTT */
543 0x00000003 /* EMC_CTT_DURATION */
544 0x0000f2f3 /* EMC_CFG_PIPE */
545 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
546 0x0000000a /* EMC_QPOP */
547 >;
548 };
549 };
550 };