| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | * Atmel Extensible Direct Memory Access Controller (XDMAC) |
| 2 | |
| 3 | * XDMA Controller |
| 4 | Required properties: |
| 5 | - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or |
| 6 | "microchip,sama7g5-dma" or |
| 7 | "microchip,sam9x7-dma", "atmel,sama5d4-dma". |
| 8 | - reg: Should contain DMA registers location and length. |
| 9 | - interrupts: Should contain DMA interrupt. |
| 10 | - #dma-cells: Must be <1>, used to represent the number of integer cells in |
| 11 | the dmas property of client devices. |
| 12 | - The 1st cell specifies the channel configuration register: |
| 13 | - bit 13: SIF, source interface identifier, used to get the memory |
| 14 | interface identifier, |
| 15 | - bit 14: DIF, destination interface identifier, used to get the peripheral |
| 16 | interface identifier, |
| 17 | - bit 30-24: PERID, peripheral identifier. |
| 18 | |
| 19 | Example: |
| 20 | |
| 21 | dma1: dma-controller@f0004000 { |
| 22 | compatible = "atmel,sama5d4-dma"; |
| 23 | reg = <0xf0004000 0x200>; |
| 24 | interrupts = <50 4 0>; |
| 25 | #dma-cells = <1>; |
| 26 | }; |
| 27 | |
| 28 | |
| 29 | * DMA clients |
| 30 | DMA clients connected to the Atmel XDMA controller must use the format |
| 31 | described in the dma.txt file, using a one-cell specifier for each channel. |
| 32 | The two cells in order are: |
| 33 | 1. A phandle pointing to the DMA controller. |
| 34 | 2. Channel configuration register. Configurable fields are: |
| 35 | - bit 13: SIF, source interface identifier, used to get the memory |
| 36 | interface identifier, |
| 37 | - bit 14: DIF, destination interface identifier, used to get the peripheral |
| 38 | interface identifier, |
| 39 | - bit 30-24: PERID, peripheral identifier. |
| 40 | |
| 41 | Example: |
| 42 | |
| 43 | i2c2: i2c@f8024000 { |
| 44 | compatible = "atmel,at91sam9x5-i2c"; |
| 45 | reg = <0xf8024000 0x4000>; |
| 46 | interrupts = <34 4 6>; |
| 47 | dmas = <&dma1 |
| 48 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| 49 | | AT91_XDMAC_DT_PERID(6))>, |
| 50 | <&dma1 |
| 51 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
| 52 | | AT91_XDMAC_DT_PERID(7))>; |
| 53 | dma-names = "tx", "rx"; |
| 54 | }; |