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git01.mediatek.com / filogic / uboot / 7230160e1bcdfcb15259c27150bd6e5fe9da2117 / . / arch / powerpc / include / asm / config.h
blob: 1b9c47bac10547020437b9cd7352d1a6b53da7a0 [file] [log] [blame]
Kumar Gala4c882892009-02-05 20:40:57 -0600[diff] [blame]1/*
Poonam Aggrwal2ba3ee02011-01-13 21:39:27 +0530[diff] [blame]2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala4c882892009-02-05 20:40:57 -0600[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_CONFIG_H_
22#define _ASM_CONFIG_H_
23
Mike Frysingera0dadf82009-11-03 11:35:59 -0500[diff] [blame]24#define CONFIG_LMB
John Rigbyeea8e692010-10-13 13:57:35 -0600[diff] [blame]25#define CONFIG_SYS_BOOT_RAMDISK_HIGH
26#define CONFIG_SYS_BOOT_GET_CMDLINE
27#define CONFIG_SYS_BOOT_GET_KBD
Mike Frysingera0dadf82009-11-03 11:35:59 -0500[diff] [blame]28
Kumar Gala4cd44a82009-02-05 20:40:58 -0600[diff] [blame]29#ifndef CONFIG_MAX_MEM_MAPPED
Becky Bruce9f75d932009-02-23 13:56:51 -0600[diff] [blame]30#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
Kumar Gala4cd44a82009-02-05 20:40:58 -0600[diff] [blame]31#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
32#else
Stefan Roesea14295e2009-02-11 09:37:12 +0100[diff] [blame]33#define CONFIG_MAX_MEM_MAPPED (256 << 20)
Kumar Gala4cd44a82009-02-05 20:40:58 -0600[diff] [blame]34#endif
35#endif
36
Peter Tyserbee01682009-07-15 00:01:08 -0500[diff] [blame]37/* Check if boards need to enable FSL DMA engine for SDRAM init */
38#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
39#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
40 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
41 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
Peter Tyserae7a7d42009-06-30 17:15:40 -0500[diff] [blame]42#define CONFIG_FSL_DMA
43#endif
Kumar Gala4c882892009-02-05 20:40:57 -0600[diff] [blame]44#endif
Peter Tyserae7a7d42009-06-30 17:15:40 -0500[diff] [blame]45
Poonam Aggrwalda3dda32009-08-20 18:55:35 +0530[diff] [blame]46#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
Kumar Gala16a276e2010-03-30 23:06:53 -0500[diff] [blame]47 defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
Poonam Aggrwalda3dda32009-08-20 18:55:35 +0530[diff] [blame]48 defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
Kumar Galabb5409c2009-03-19 02:39:17 -0500[diff] [blame]49#define CONFIG_MAX_CPUS 2
Kumar Galabd29be82010-06-01 10:29:11 -0500[diff] [blame]50#elif defined(CONFIG_PPC_P2040)
51#define CONFIG_MAX_CPUS 4
Kumar Galaf2134b82010-01-27 10:26:46 -0600[diff] [blame]52#elif defined(CONFIG_PPC_P3041)
53#define CONFIG_MAX_CPUS 4
Kumar Galabb5409c2009-03-19 02:39:17 -0500[diff] [blame]54#elif defined(CONFIG_PPC_P4080)
55#define CONFIG_MAX_CPUS 8
Kumar Gala7ee3d942009-10-21 13:32:58 -0500[diff] [blame]56#elif defined(CONFIG_PPC_P5020)
57#define CONFIG_MAX_CPUS 2
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530[diff] [blame]58#else
Kumar Galabb5409c2009-03-19 02:39:17 -0500[diff] [blame]59#define CONFIG_MAX_CPUS 1
Poonam Aggrwal4baef822009-07-31 12:08:14 +0530[diff] [blame]60#endif
61
Peter Tyser7feaacb2009-10-23 15:55:47 -0500[diff] [blame]62/*
63 * Provide a default boot page translation virtual address that lines up with
64 * Freescale's default e500 reset page.
65 */
66#if (defined(CONFIG_E500) && defined(CONFIG_MP))
67#ifndef CONFIG_BPTR_VIRT_ADDR
68#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
69#endif
70#endif
71
Kumar Gala2e972932009-10-31 11:23:41 -0500[diff] [blame]72/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
73#if defined(CONFIG_TSEC_ENET) && \
Poonam Aggrwalb07a7de2011-01-13 21:40:05 +0530[diff] [blame]74 (defined(CONFIG_P1010) || defined(CONFIG_P1014) || \
Poonam Aggrwal2ba3ee02011-01-13 21:39:27 +0530[diff] [blame]75 defined(CONFIG_P1020) || defined(CONFIG_P1011))
Kumar Gala2e972932009-10-31 11:23:41 -0500[diff] [blame]76#define CONFIG_TSECV2
77#endif
78
Kim Phillipsdef125f2010-06-01 12:24:27 -0500[diff] [blame]79/*
80 * SEC (crypto unit) major compatible version determination
81 */
Poonam Aggrwal2ba3ee02011-01-13 21:39:27 +0530[diff] [blame]82#if defined(CONFIG_FSL_CORENET) || \
Poonam Aggrwalb07a7de2011-01-13 21:40:05 +0530[diff] [blame]83 defined(CONFIG_P1010) || defined(CONFIG_P1014)
Kim Phillips1b625492010-06-01 12:24:34 -0500[diff] [blame]84#define CONFIG_SYS_FSL_SEC_COMPAT 4
85#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
Kim Phillipsdef125f2010-06-01 12:24:27 -0500[diff] [blame]86#define CONFIG_SYS_FSL_SEC_COMPAT 2
87#endif
88
Kumar Gala42f99182009-11-12 10:26:16 -0600[diff] [blame]89/* Number of TLB CAM entries we have on FSL Book-E chips */
90#if defined(CONFIG_E500MC)
91#define CONFIG_SYS_NUM_TLBCAMS 64
92#elif defined(CONFIG_E500)
93#define CONFIG_SYS_NUM_TLBCAMS 16
94#endif
95
Becky Bruce0d4cee12010-06-17 11:37:20 -0500[diff] [blame]96/* Since so many PPC SOCs have a semi-common LBC, define this here */
97#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
98 defined(CONFIG_MPC83xx)
99#define CONFIG_FSL_LBC
100#endif
101
Albert Aribaud036c6b42010-08-08 05:17:05 +0530[diff] [blame]102/* All PPC boards must swap IDE bytes */
103#define CONFIG_IDE_SWAP_IO
104
Peter Tyserae7a7d42009-06-30 17:15:40 -0500[diff] [blame]105#endif /* _ASM_CONFIG_H_ */