Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG |
| 4 | * Patrick Bruenn <p.bruenn@beckhoff.com> |
| 5 | * |
| 6 | * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c |
| 7 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 11 | #include <asm/arch/sys_proto.h> |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 12 | #include <asm/arch/clock.h> |
| 13 | #include <asm/arch/iomux-mx53.h> |
Stefano Babic | 33731bc | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 14 | #include <asm/mach-imx/mx5_video.h> |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 15 | #include <ACEX1K.h> |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 16 | #include <asm/gpio.h> |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 17 | |
| 18 | enum LED_GPIOS { |
| 19 | GPIO_SD1_CD = IMX_GPIO_NR(1, 1), |
| 20 | GPIO_SD2_CD = IMX_GPIO_NR(1, 4), |
| 21 | GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16), |
| 22 | GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17), |
| 23 | GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18), |
| 24 | GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19), |
| 25 | GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20), |
| 26 | GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21), |
| 27 | GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22), |
| 28 | GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23), |
| 29 | GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24), |
| 30 | GPIO_SUPS_INT = IMX_GPIO_NR(3, 31), |
| 31 | GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8), |
| 32 | GPIO_C3_STATUS = IMX_GPIO_NR(6, 7), |
| 33 | GPIO_C3_DONE = IMX_GPIO_NR(6, 9), |
| 34 | }; |
| 35 | |
| 36 | #define CCAT_BASE_ADDR ((void *)0xf0000000) |
| 37 | #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32)) |
| 38 | #define CCAT_SIZE 1191788 |
| 39 | #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12) |
| 40 | static const char CCAT_SIGNATURE[] = "CCAT"; |
| 41 | |
| 42 | static const u32 CCAT_MODE_CONFIG = 0x0024DC81; |
| 43 | static const u32 CCAT_MODE_RUN = 0x0033DC8F; |
| 44 | |
| 45 | DECLARE_GLOBAL_DATA_PTR; |
| 46 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 47 | u32 get_board_rev(void) |
| 48 | { |
| 49 | struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; |
| 50 | struct fuse_bank *bank = &iim->bank[0]; |
| 51 | struct fuse_bank0_regs *fuse = |
| 52 | (struct fuse_bank0_regs *)bank->fuse_regs; |
| 53 | |
| 54 | int rev = readl(&fuse->gp[6]); |
| 55 | |
| 56 | return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; |
| 57 | } |
| 58 | |
| 59 | /* |
| 60 | * Set CCAT mode |
| 61 | * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN |
| 62 | */ |
| 63 | void weim_cs0_settings(u32 mode) |
| 64 | { |
| 65 | struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; |
| 66 | |
| 67 | writel(0x0, &weim_regs->cs0gcr1); |
| 68 | writel(mode, &weim_regs->cs0gcr1); |
| 69 | writel(0x00001002, &weim_regs->cs0gcr2); |
| 70 | |
| 71 | writel(0x04000000, &weim_regs->cs0rcr1); |
| 72 | writel(0x00000000, &weim_regs->cs0rcr2); |
| 73 | |
| 74 | writel(0x04000000, &weim_regs->cs0wcr1); |
| 75 | writel(0x00000000, &weim_regs->cs0wcr2); |
| 76 | } |
| 77 | |
| 78 | static void setup_gpio_eim(void) |
| 79 | { |
Steffen Dirkwinkel | 098e9ef | 2019-04-17 13:57:14 +0200 | [diff] [blame] | 80 | gpio_request(GPIO_C3_STATUS, "GPIO_C3_STATUS"); |
| 81 | gpio_request(GPIO_C3_DONE, "GPIO_C3_DONE"); |
| 82 | gpio_request(GPIO_C3_CONFIG, "GPIO_C3_CONFIG"); |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 83 | gpio_direction_input(GPIO_C3_STATUS); |
| 84 | gpio_direction_input(GPIO_C3_DONE); |
| 85 | gpio_direction_output(GPIO_C3_CONFIG, 1); |
| 86 | |
| 87 | weim_cs0_settings(CCAT_MODE_RUN); |
| 88 | } |
| 89 | |
| 90 | static void setup_gpio_sups(void) |
| 91 | { |
Steffen Dirkwinkel | 098e9ef | 2019-04-17 13:57:14 +0200 | [diff] [blame] | 92 | gpio_request(GPIO_SUPS_INT, "GPIO_SUPS_INT"); |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 93 | gpio_direction_input(GPIO_SUPS_INT); |
| 94 | |
| 95 | static const int BLINK_INTERVALL = 50000; |
| 96 | int status = 1; |
| 97 | while (gpio_get_value(GPIO_SUPS_INT)) { |
| 98 | /* signal "CX SUPS power fail" */ |
| 99 | gpio_set_value(GPIO_LED_PWR_R, |
| 100 | (++status / BLINK_INTERVALL) % 2); |
| 101 | } |
| 102 | |
| 103 | /* signal "CX power up" */ |
| 104 | gpio_set_value(GPIO_LED_PWR_R, 1); |
| 105 | } |
| 106 | |
| 107 | static void setup_gpio_leds(void) |
| 108 | { |
Steffen Dirkwinkel | 098e9ef | 2019-04-17 13:57:14 +0200 | [diff] [blame] | 109 | gpio_request(GPIO_LED_SD2_R, "GPIO_LED_SD2_R"); |
| 110 | gpio_request(GPIO_LED_SD2_B, "GPIO_LED_SD2_B"); |
| 111 | gpio_request(GPIO_LED_SD2_G, "GPIO_LED_SD2_G"); |
| 112 | gpio_request(GPIO_LED_SD1_R, "GPIO_LED_SD1_R"); |
| 113 | gpio_request(GPIO_LED_SD1_B, "GPIO_LED_SD1_B"); |
| 114 | gpio_request(GPIO_LED_SD1_G, "GPIO_LED_SD1_G"); |
| 115 | gpio_request(GPIO_LED_PWR_R, "GPIO_LED_PWR_R"); |
| 116 | gpio_request(GPIO_LED_PWR_B, "GPIO_LED_PWR_B"); |
| 117 | gpio_request(GPIO_LED_PWR_G, "GPIO_LED_PWR_G"); |
| 118 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 119 | gpio_direction_output(GPIO_LED_SD2_R, 0); |
| 120 | gpio_direction_output(GPIO_LED_SD2_B, 0); |
| 121 | gpio_direction_output(GPIO_LED_SD2_G, 0); |
| 122 | gpio_direction_output(GPIO_LED_SD1_R, 0); |
| 123 | gpio_direction_output(GPIO_LED_SD1_B, 0); |
| 124 | gpio_direction_output(GPIO_LED_SD1_G, 0); |
| 125 | gpio_direction_output(GPIO_LED_PWR_R, 0); |
| 126 | gpio_direction_output(GPIO_LED_PWR_B, 0); |
| 127 | gpio_direction_output(GPIO_LED_PWR_G, 0); |
| 128 | } |
| 129 | |
| 130 | #ifdef CONFIG_USB_EHCI_MX5 |
| 131 | int board_ehci_hcd_init(int port) |
| 132 | { |
| 133 | /* request VBUS power enable pin, GPIO7_8 */ |
| 134 | gpio_direction_output(IMX_GPIO_NR(7, 8), 1); |
| 135 | return 0; |
| 136 | } |
| 137 | #endif |
| 138 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 139 | |
| 140 | static int power_init(void) |
| 141 | { |
| 142 | /* nothing to do on CX9020 */ |
| 143 | return 0; |
| 144 | } |
| 145 | |
| 146 | static void clock_1GHz(void) |
| 147 | { |
| 148 | int ret; |
| 149 | u32 ref_clk = MXC_HCLK; |
| 150 | /* |
| 151 | * After increasing voltage to 1.25V, we can switch |
| 152 | * CPU clock to 1GHz and DDR to 400MHz safely |
| 153 | */ |
| 154 | ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); |
| 155 | if (ret) |
| 156 | printf("CPU: Switch CPU clock to 1GHZ failed\n"); |
| 157 | |
| 158 | ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); |
| 159 | ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); |
| 160 | if (ret) |
| 161 | printf("CPU: Switch DDR clock to 400MHz failed\n"); |
| 162 | } |
| 163 | |
| 164 | int board_early_init_f(void) |
| 165 | { |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 166 | |
| 167 | return 0; |
| 168 | } |
| 169 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 170 | int board_init(void) |
| 171 | { |
| 172 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
| 173 | |
| 174 | mxc_set_sata_internal_clock(); |
| 175 | |
Steffen Dirkwinkel | 098e9ef | 2019-04-17 13:57:14 +0200 | [diff] [blame] | 176 | setup_gpio_leds(); |
| 177 | setup_gpio_sups(); |
| 178 | setup_gpio_eim(); |
| 179 | setup_iomux_lcd(); |
| 180 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | int checkboard(void) |
| 185 | { |
| 186 | puts("Board: Beckhoff CX9020\n"); |
| 187 | |
| 188 | return 0; |
| 189 | } |
| 190 | |
| 191 | static int ccat_config_fn(int assert_config, int flush, int cookie) |
| 192 | { |
| 193 | /* prepare FPGA for programming */ |
| 194 | weim_cs0_settings(CCAT_MODE_CONFIG); |
| 195 | gpio_set_value(GPIO_C3_CONFIG, 0); |
| 196 | udelay(1); |
| 197 | gpio_set_value(GPIO_C3_CONFIG, 1); |
| 198 | udelay(230); |
| 199 | |
| 200 | return FPGA_SUCCESS; |
| 201 | } |
| 202 | |
| 203 | static int ccat_status_fn(int cookie) |
| 204 | { |
| 205 | return FPGA_FAIL; |
| 206 | } |
| 207 | |
| 208 | static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie) |
| 209 | { |
| 210 | const uint8_t *const buffer = buf; |
| 211 | |
| 212 | /* program CCAT */ |
| 213 | int i; |
| 214 | for (i = 0; i < buf_len; ++i) |
| 215 | writeb(buffer[i], CCAT_BASE_ADDR); |
| 216 | |
| 217 | writeb(0xff, CCAT_BASE_ADDR); |
| 218 | writeb(0xff, CCAT_BASE_ADDR); |
| 219 | |
| 220 | return FPGA_SUCCESS; |
| 221 | } |
| 222 | |
| 223 | static int ccat_done_fn(int cookie) |
| 224 | { |
| 225 | /* programming complete? */ |
| 226 | return gpio_get_value(GPIO_C3_DONE); |
| 227 | } |
| 228 | |
| 229 | static int ccat_post_fn(int cookie) |
| 230 | { |
| 231 | /* switch to FPGA run mode */ |
| 232 | weim_cs0_settings(CCAT_MODE_RUN); |
| 233 | invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR); |
| 234 | |
| 235 | if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) { |
| 236 | printf("Verifing CCAT firmware failed, signature not found\n"); |
| 237 | return FPGA_FAIL; |
| 238 | } |
| 239 | |
| 240 | /* signal "CX booting OS" */ |
| 241 | gpio_set_value(GPIO_LED_PWR_R, 1); |
| 242 | gpio_set_value(GPIO_LED_PWR_G, 1); |
| 243 | gpio_set_value(GPIO_LED_PWR_B, 0); |
| 244 | return FPGA_SUCCESS; |
| 245 | } |
| 246 | |
| 247 | static Altera_CYC2_Passive_Serial_fns ccat_fns = { |
| 248 | .config = ccat_config_fn, |
| 249 | .status = ccat_status_fn, |
| 250 | .done = ccat_done_fn, |
| 251 | .write = ccat_write_fn, |
| 252 | .abort = ccat_post_fn, |
| 253 | .post = ccat_post_fn, |
| 254 | }; |
| 255 | |
| 256 | static Altera_desc ccat_fpga = { |
| 257 | .family = Altera_CYC2, |
| 258 | .iface = passive_serial, |
| 259 | .size = CCAT_SIZE, |
| 260 | .iface_fns = &ccat_fns, |
| 261 | .base = CCAT_BASE_ADDR, |
| 262 | }; |
| 263 | |
| 264 | int board_late_init(void) |
| 265 | { |
| 266 | if (!power_init()) |
| 267 | clock_1GHz(); |
| 268 | |
| 269 | fpga_init(); |
| 270 | fpga_add(fpga_altera, &ccat_fpga); |
| 271 | |
| 272 | return 0; |
| 273 | } |