blob: 12fb87441e0a499a2faa3ceae933630566b663ad [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ryan Mallon50515fa2011-06-05 07:21:22 +00002/*
3 * Bluewater Systems Snapper 9260/9G20 modules
4 *
5 * (C) Copyright 2011 Bluewater Systems
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
Ryan Mallon50515fa2011-06-05 07:21:22 +00008 */
9
10#include <common.h>
Simon Glass6d20e072014-10-29 13:09:01 -060011#include <dm.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070012#include <init.h>
Ryan Mallon50515fa2011-06-05 07:21:22 +000013#include <asm/io.h>
Simon Glass6d20e072014-10-29 13:09:01 -060014#include <asm/gpio.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060015#include <asm/mach-types.h>
Ryan Mallon50515fa2011-06-05 07:21:22 +000016#include <asm/arch/at91sam9260_matrix.h>
17#include <asm/arch/at91sam9_smc.h>
18#include <asm/arch/at91_common.h>
Wenyou Yang78f89762016-02-03 10:16:50 +080019#include <asm/arch/clk.h>
Ryan Mallon50515fa2011-06-05 07:21:22 +000020#include <asm/arch/gpio.h>
Simon Glass6d20e072014-10-29 13:09:01 -060021#include <asm/arch/atmel_serial.h>
Ryan Mallon50515fa2011-06-05 07:21:22 +000022#include <net.h>
23#include <netdev.h>
24#include <i2c.h>
25#include <pca953x.h>
Simon Glassdbd79542020-05-10 11:40:11 -060026#include <linux/delay.h>
Ryan Mallon50515fa2011-06-05 07:21:22 +000027
28DECLARE_GLOBAL_DATA_PTR;
29
30/* IO Expander pins */
31#define IO_EXP_ETH_RESET (0 << 1)
32#define IO_EXP_ETH_POWER (1 << 1)
33
34static void macb_hw_init(void)
35{
Ryan Mallon50515fa2011-06-05 07:21:22 +000036 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
Ryan Mallon50515fa2011-06-05 07:21:22 +000037
Wenyou Yang78f89762016-02-03 10:16:50 +080038 at91_periph_clk_enable(ATMEL_ID_EMAC0);
Ryan Mallon50515fa2011-06-05 07:21:22 +000039
40 /* Disable pull-ups to prevent PHY going into test mode */
41 writel(pin_to_mask(AT91_PIN_PA14) |
42 pin_to_mask(AT91_PIN_PA15) |
43 pin_to_mask(AT91_PIN_PA18),
44 &pioa->pudr);
45
46 /* Power down ethernet */
47 pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
48 pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
49
50 /* Hold ethernet in reset */
51 pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
52 pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
53
54 /* Enable ethernet power */
55 pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
56
Heiko Schocher8a84ae12013-11-18 08:07:23 +010057 at91_phy_reset();
Ryan Mallon50515fa2011-06-05 07:21:22 +000058
59 /* Bring the ethernet out of reset */
60 pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
61
62 /* The phy internal reset take 21ms */
63 udelay(21 * 1000);
64
65 /* Re-enable pull-up */
66 writel(pin_to_mask(AT91_PIN_PA14) |
67 pin_to_mask(AT91_PIN_PA15) |
68 pin_to_mask(AT91_PIN_PA18),
69 &pioa->puer);
70
71 at91_macb_hw_init();
72}
73
74static void nand_hw_init(void)
75{
76 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
77 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
78 unsigned long csa;
79
80 /* Enable CS3 as NAND/SmartMedia */
81 csa = readl(&matrix->ebicsa);
82 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
83 writel(csa, &matrix->ebicsa);
84
85 /* Configure SMC CS3 for NAND/SmartMedia */
86 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
87 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
88 &smc->cs[3].setup);
89 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
90 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
91 &smc->cs[3].pulse);
92 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
93 &smc->cs[3].cycle);
94 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
95 AT91_SMC_MODE_EXNW_DISABLE |
96 AT91_SMC_MODE_DBW_8 |
97 AT91_SMC_MODE_TDF_CYCLE(3),
98 &smc->cs[3].mode);
99
100 /* Configure RDY/BSY */
Simon Glass6d20e072014-10-29 13:09:01 -0600101 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
102 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
Ryan Mallon50515fa2011-06-05 07:21:22 +0000103
104 /* Enable NandFlash */
Simon Glass6d20e072014-10-29 13:09:01 -0600105 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
106 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Ryan Mallon50515fa2011-06-05 07:21:22 +0000107}
108
109int board_init(void)
110{
Wenyou Yang78f89762016-02-03 10:16:50 +0800111 at91_periph_clk_enable(ATMEL_ID_PIOA);
112 at91_periph_clk_enable(ATMEL_ID_PIOB);
113 at91_periph_clk_enable(ATMEL_ID_PIOC);
Ryan Mallon50515fa2011-06-05 07:21:22 +0000114
115 /* The mach-type is the same for both Snapper 9260 and 9G20 */
116 gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
117
118 /* Address of boot parameters */
119 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
120
121 /* Initialise peripherals */
122 at91_seriald_hw_init();
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100123 i2c_set_bus_num(0);
Ryan Mallon50515fa2011-06-05 07:21:22 +0000124 nand_hw_init();
125 macb_hw_init();
126
127 return 0;
128}
129
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900130int board_eth_init(struct bd_info *bis)
Ryan Mallon50515fa2011-06-05 07:21:22 +0000131{
132 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
133}
134
135int dram_init(void)
136{
137 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
138 CONFIG_SYS_SDRAM_SIZE);
139 return 0;
140}
141
142void reset_phy(void)
143{
144}
Simon Glass6d20e072014-10-29 13:09:01 -0600145
146static struct atmel_serial_platdata at91sam9260_serial_plat = {
147 .base_addr = ATMEL_BASE_DBGU,
148};
149
150U_BOOT_DEVICE(at91sam9260_serial) = {
151 .name = "serial_atmel",
Simon Glass71fa5b42020-12-03 16:55:18 -0700152 .plat = &at91sam9260_serial_plat,
Simon Glass6d20e072014-10-29 13:09:01 -0600153};