| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2017 Intel Corporation. |
| 4 | */ |
| 5 | |
| 6 | #ifndef ASM_FAST_SPI_H |
| 7 | #define ASM_FAST_SPI_H |
| 8 | |
| 9 | /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ |
| Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 10 | #include <linux/bitops.h> |
| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 11 | struct fast_spi_regs { |
| 12 | u32 bfp; |
| 13 | u32 hsfsts_ctl; |
| 14 | u32 faddr; |
| 15 | u32 dlock; |
| 16 | |
| 17 | u32 fdata[0x10]; |
| 18 | |
| 19 | u32 fracc; |
| 20 | u32 freg[12]; |
| 21 | u32 fpr[5]; |
| 22 | u32 gpr0; |
| 23 | u32 spare2; |
| 24 | u32 sts_ctl; |
| 25 | u16 preop; |
| 26 | u16 optype; |
| 27 | u8 opmenu[8]; |
| 28 | |
| 29 | u32 spare3; |
| 30 | u32 fdoc; |
| 31 | u32 fdod; |
| 32 | u32 spare4; |
| 33 | u32 afc; |
| 34 | u32 vscc[2]; |
| 35 | u32 ptinx; |
| 36 | u32 ptdata; |
| 37 | }; |
| 38 | check_member(fast_spi_regs, ptdata, 0xd0); |
| 39 | |
| 40 | /* Bit definitions for BFPREG (0x00) register */ |
| 41 | #define SPIBAR_BFPREG_PRB_MASK 0x7fff |
| 42 | #define SPIBAR_BFPREG_PRL_SHIFT 16 |
| 43 | #define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) |
| 44 | |
| 45 | /* PCI configuration registers */ |
| 46 | #define SPIBAR_BIOS_CONTROL 0xdc |
| 47 | #define SPIBAR_BIOS_CONTROL_WPD BIT(0) |
| 48 | #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE BIT(1) |
| 49 | #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE BIT(2) |
| 50 | #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE BIT(3) |
| 51 | #define SPIBAR_BIOS_CONTROL_EISS BIT(5) |
| 52 | #define SPIBAR_BIOS_CONTROL_BILD BIT(7) |
| 53 | |
| 54 | /** |
| 55 | * fast_spi_get_bios_mmap() - Get memory map for SPI flash |
| 56 | * |
| 57 | * @pdev: PCI device to use (this is the Fast SPI device) |
| 58 | * @map_basep: Returns base memory address for mapped SPI |
| 59 | * @map_sizep: Returns size of mapped SPI |
| 60 | * @offsetp: Returns start offset of SPI flash where the map works |
| 61 | * correctly (offsets before this are not visible) |
| 62 | * @return 0 (always) |
| 63 | */ |
| 64 | int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep, |
| 65 | uint *offsetp); |
| 66 | |
| Simon Glass | 6c7799b | 2020-05-27 06:58:46 -0600 | [diff] [blame] | 67 | /** |
| 68 | * fast_spi_get_bios_mmap_regs() - Get memory map for SPI flash given regs |
| 69 | * |
| 70 | * @regs: SPI registers to use |
| 71 | * @map_basep: Returns base memory address for mapped SPI |
| 72 | * @map_sizep: Returns size of mapped SPI |
| 73 | * @offsetp: Returns start offset of SPI flash where the map works |
| 74 | * correctly (offsets before this are not visible) |
| 75 | * @return 0 (always) |
| 76 | */ |
| 77 | int fast_spi_get_bios_mmap_regs(struct fast_spi_regs *regs, ulong *map_basep, |
| 78 | uint *map_sizep, uint *offsetp); |
| 79 | |
| 80 | /** |
| 81 | * fast_spi_early_init() - Set up a BAR to use SPI early in U-Boot |
| 82 | * |
| 83 | * @pdev: PCI device to use (this is the Fast SPI device) |
| 84 | * @mmio_base: MMIO base to use to access registers |
| 85 | */ |
| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 86 | int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base); |
| 87 | |
| 88 | #endif /* ASM_FAST_SPI_H */ |