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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mingkai Huf354b532011-07-07 12:29:15 +08002/*
ramneek mehresh3d339632012-04-18 19:39:53 +00003 * Copyright 2011,2012 Freescale Semiconductor, Inc.
Mingkai Huf354b532011-07-07 12:29:15 +08004 */
5
6#include <common.h>
7#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -06008#include <env.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -07009#include <fdt_support.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060010#include <image.h>
Simon Glassa7b51302019-11-14 12:57:46 -070011#include <init.h>
Mingkai Huf354b532011-07-07 12:29:15 +080012#include <netdev.h>
13#include <linux/compiler.h>
14#include <asm/mmu.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/immap_85xx.h>
18#include <asm/fsl_law.h>
19#include <asm/fsl_serdes.h>
Mingkai Huf354b532011-07-07 12:29:15 +080020#include <asm/fsl_liodn.h>
Mingkai Hu4c46d822011-07-19 16:20:13 +080021#include <fm_eth.h>
Mingkai Huf354b532011-07-07 12:29:15 +080022
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090023extern void pci_of_setup(void *blob, struct bd_info *bd);
Mingkai Huf354b532011-07-07 12:29:15 +080024
25#include "cpld.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29int checkboard(void)
30{
31 u8 sw;
Simon Glassa8b57392012-12-13 20:48:48 +000032 struct cpu_type *cpu = gd->arch.cpu;
Mingkai Huf354b532011-07-07 12:29:15 +080033 unsigned int i;
34
35 printf("Board: %sRDB, ", cpu->name);
36 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
37 CPLD_READ(cpld_ver_sub));
38
39 sw = CPLD_READ(fbank_sel);
40 printf("vBank: %d\n", sw & 0x1);
41
Mingkai Huf354b532011-07-07 12:29:15 +080042 /*
Mingkai Huf354b532011-07-07 12:29:15 +080043 * Display the actual SERDES reference clocks as configured by the
44 * dip switches on the board. Note that the SWx registers could
45 * technically be set to force the reference clocks to match the
46 * values that the SERDES expects (or vice versa). For now, however,
47 * we just display both values and hope the user notices when they
48 * don't match.
49 */
50 puts("SERDES Reference Clocks: ");
51 sw = in_8(&CPLD_SW(2)) >> 2;
52 for (i = 0; i < 2; i++) {
Shaohui Xieab9e5e62011-12-02 09:38:12 +080053 static const char * const freq[][3] = {{"0", "100", "125"},
54 {"100", "156.25", "125"}
55 };
Mingkai Huf354b532011-07-07 12:29:15 +080056 unsigned int clock = (sw >> (2 * i)) & 3;
57
Shaohui Xieab9e5e62011-12-02 09:38:12 +080058 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
Mingkai Huf354b532011-07-07 12:29:15 +080059 }
60 puts("\n");
61
62 return 0;
63}
64
65int board_early_init_f(void)
66{
67 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68
69 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
70 setbits_be32(&gur->ddrclkdr, 0x000f000f);
71
72 return 0;
73}
74
Shaohui Xie498610c2012-12-03 21:36:32 +000075#define CPLD_LANE_A_SEL 0x1
76#define CPLD_LANE_G_SEL 0x2
77#define CPLD_LANE_C_SEL 0x4
78#define CPLD_LANE_D_SEL 0x8
79
80void board_config_lanes_mux(void)
81{
82 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
83 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
84 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
85
86 u8 mux = 0;
87 switch (srds_prtcl) {
88 case 0x2:
89 case 0x5:
90 case 0x9:
91 case 0xa:
92 case 0xf:
93 break;
94 case 0x8:
95 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
96 break;
97 case 0x14:
98 mux |= CPLD_LANE_A_SEL;
99 break;
100 case 0x17:
101 mux |= CPLD_LANE_G_SEL;
102 break;
103 case 0x16:
104 case 0x19:
105 case 0x1a:
106 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
107 break;
108 case 0x1c:
109 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
110 break;
111 default:
112 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
113 break;
114 }
115 CPLD_WRITE(serdes_mux, mux);
116}
117
Mingkai Huf354b532011-07-07 12:29:15 +0800118int board_early_init_r(void)
119{
120 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun220c3462014-06-24 21:16:20 -0700121 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Mingkai Huf354b532011-07-07 12:29:15 +0800122
123 /*
124 * Remap Boot flash + PROMJET region to caching-inhibited
125 * so that flash can be erased properly.
126 */
127
128 /* Flush d-cache and invalidate i-cache of any FLASH data */
129 flush_dcache();
130 invalidate_icache();
131
York Sun220c3462014-06-24 21:16:20 -0700132 if (flash_esel == -1) {
133 /* very unlikely unless something is messed up */
134 puts("Error: Could not find TLB for FLASH BASE\n");
135 flash_esel = 2; /* give our best effort to continue */
136 } else {
137 /* invalidate existing TLB entry for flash + promjet */
138 disable_tlb(flash_esel);
139 }
Mingkai Huf354b532011-07-07 12:29:15 +0800140
141 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
142 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
143 0, flash_esel, BOOKE_PAGESZ_256M, 1);
144
Shaohui Xie498610c2012-12-03 21:36:32 +0000145 board_config_lanes_mux();
Mingkai Huf354b532011-07-07 12:29:15 +0800146
147 return 0;
148}
149
Shaohui Xieada02612011-09-13 17:55:11 +0800150unsigned long get_board_sys_clk(unsigned long dummy)
151{
152 u8 sysclk_conf = CPLD_READ(sysclk_sw1);
153
154 switch (sysclk_conf & 0x7) {
155 case CPLD_SYSCLK_83:
156 return 83333333;
157 case CPLD_SYSCLK_100:
158 return 100000000;
159 default:
160 return 66666666;
161 }
162}
163
Mingkai Huf354b532011-07-07 12:29:15 +0800164#define NUM_SRDS_BANKS 2
165
166int misc_init_r(void)
167{
168 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
169 u32 actual[NUM_SRDS_BANKS];
170 unsigned int i;
171 u8 sw;
Shaohui Xieab9e5e62011-12-02 09:38:12 +0800172 static const int freq[][3] = {
173 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
174 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
175 SRDS_PLLCR0_RFCK_SEL_125}
176 };
Mingkai Huf354b532011-07-07 12:29:15 +0800177
178 sw = in_8(&CPLD_SW(2)) >> 2;
179 for (i = 0; i < NUM_SRDS_BANKS; i++) {
180 unsigned int clock = (sw >> (2 * i)) & 3;
Shaohui Xieab9e5e62011-12-02 09:38:12 +0800181 if (clock == 0x3) {
Mingkai Huf354b532011-07-07 12:29:15 +0800182 printf("Warning: SDREFCLK%u switch setting of '11' is "
183 "unsupported\n", i + 1);
184 break;
185 }
Shaohui Xieab9e5e62011-12-02 09:38:12 +0800186 if (i == 0 && clock == 0)
187 puts("Warning: SDREFCLK1 switch setting of"
188 "'00' is unsupported\n");
189 else
190 actual[i] = freq[i][clock];
Shaohui Xie6d14b422013-03-25 07:40:18 +0000191
192 /*
193 * PC board uses a different CPLD with PB board, this CPLD
194 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
195 * board has cpld_ver_sub = 0, and pcba_ver = 4.
196 */
197 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
198 (CPLD_READ(pcba_ver) == 5)) {
199 /* PC board bank2 frequency */
200 actual[i] = freq[i-1][clock];
201 }
Mingkai Huf354b532011-07-07 12:29:15 +0800202 }
203
204 for (i = 0; i < NUM_SRDS_BANKS; i++) {
205 u32 expected = in_be32(&regs->bank[i].pllcr0);
206 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
207 if (expected != actual[i]) {
208 printf("Warning: SERDES bank %u expects reference clock"
209 " %sMHz, but actual is %sMHz\n", i + 1,
210 serdes_clock_to_string(expected),
211 serdes_clock_to_string(actual[i]));
212 }
213 }
214
215 return 0;
216}
217
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900218int ft_board_setup(void *blob, struct bd_info *bd)
Mingkai Huf354b532011-07-07 12:29:15 +0800219{
220 phys_addr_t base;
221 phys_size_t size;
222
223 ft_cpu_setup(blob, bd);
224
Simon Glassda1a1342017-08-03 12:22:15 -0600225 base = env_get_bootm_low();
226 size = env_get_bootm_size();
Mingkai Huf354b532011-07-07 12:29:15 +0800227
228 fdt_fixup_memory(blob, (u64)base, (u64)size);
229
ramneek mehresh3d339632012-04-18 19:39:53 +0000230#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Sriram Dash9fd465c2016-09-16 17:12:15 +0530231 fsl_fdt_fixup_dr_usb(blob, bd);
ramneek mehresh3d339632012-04-18 19:39:53 +0000232#endif
233
Mingkai Huf354b532011-07-07 12:29:15 +0800234#ifdef CONFIG_PCI
235 pci_of_setup(blob, bd);
236#endif
237
238 fdt_fixup_liodn(blob);
Mingkai Hu4c46d822011-07-19 16:20:13 +0800239#ifdef CONFIG_SYS_DPAA_FMAN
Madalin Bucur70848512020-04-30 15:59:58 +0300240#ifndef CONFIG_DM_ETH
Mingkai Hu4c46d822011-07-19 16:20:13 +0800241 fdt_fixup_fman_ethernet(blob);
242#endif
Madalin Bucur70848512020-04-30 15:59:58 +0300243#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600244
245 return 0;
Mingkai Huf354b532011-07-07 12:29:15 +0800246}