Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000-2003 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 5 | * |
| 6 | * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com) |
| 7 | * |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 8 | * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
Simon Glass | 0ffd9db | 2019-12-28 10:45:06 -0700 | [diff] [blame] | 12 | #include <init.h> |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 13 | #include <asm/immap.h> |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 14 | #include <asm/io.h> |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 15 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 18 | #define PERIOD 13 /* system bus period in ns */ |
| 19 | #define SDRAM_TREFI 7800 /* in ns */ |
| 20 | |
| 21 | int checkboard(void) |
| 22 | { |
| 23 | puts("Board: "); |
| 24 | puts("Freescale MCF5275 EVB\n"); |
| 25 | return 0; |
| 26 | }; |
| 27 | |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 28 | int dram_init(void) |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 29 | { |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 30 | sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); |
| 31 | gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 32 | |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 33 | /* Enable SDRAM */ |
| 34 | out_be16(&gpio_reg->par_sdram, 0x3FF); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 35 | |
| 36 | /* Set up chip select */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 37 | out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); |
| 38 | out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 39 | |
| 40 | /* Set up timing */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 41 | out_be32(&sdp->sdcfg1, 0x83711630); |
| 42 | out_be32(&sdp->sdcfg2, 0x46770000); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 43 | |
| 44 | /* Enable clock */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 45 | out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 46 | |
| 47 | /* Set precharge */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 48 | setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 49 | |
| 50 | /* Dummy write to start SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 51 | *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 52 | |
| 53 | /* Send LEMR */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 54 | setbits_be32(&sdp->sdmr, |
| 55 | MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | |
| 56 | MCF_SDRAMC_SDMR_CMD); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 58 | |
| 59 | /* Send LMR */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 60 | out_be32(&sdp->sdmr, 0x058d0000); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 62 | |
| 63 | /* Stop sending commands */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 64 | clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 65 | |
| 66 | /* Set precharge */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 67 | setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 69 | |
| 70 | /* Stop manual precharge, send 2 IREF */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 71 | clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); |
| 72 | setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; |
| 74 | *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 75 | |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 76 | |
| 77 | out_be32(&sdp->sdmr, 0x018d0000); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 79 | |
| 80 | /* Stop sending commands */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 81 | clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); |
| 82 | clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 83 | |
| 84 | /* Turn on auto refresh, lock SDMR */ |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 85 | out_be32(&sdp->sdcr, |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 86 | MCF_SDRAMC_SDCR_CKE |
| 87 | | MCF_SDRAMC_SDCR_REF |
| 88 | | MCF_SDRAMC_SDCR_MUX(1) |
| 89 | /* 1 added to round up */ |
| 90 | | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) |
Alison Wang | 95bed1f | 2012-03-26 21:49:04 +0000 | [diff] [blame] | 91 | | MCF_SDRAMC_SDCR_DQS_OE(0x3)); |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 92 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 93 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
| 94 | |
| 95 | return 0; |
Matthew Fettke | 9f3b3bb | 2008-01-24 14:02:32 -0600 | [diff] [blame] | 96 | }; |
| 97 | |
| 98 | int testdram(void) |
| 99 | { |
| 100 | /* TODO: XXX XXX XXX */ |
| 101 | printf("DRAM test not implemented!\n"); |
| 102 | |
| 103 | return (0); |
| 104 | } |