Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011, Marvell Semiconductor Inc. |
| 3 | * Lei Wen <leiwen@marvell.com> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 6 | * |
| 7 | * Back ported to the 8xx platform (from the 8260 platform) by |
| 8 | * Murray.Jensen@cmst.csiro.au, 27-Jan-01. |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <malloc.h> |
| 13 | #include <mmc.h> |
| 14 | #include <sdhci.h> |
| 15 | |
| 16 | void *aligned_buffer; |
| 17 | |
| 18 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
| 19 | { |
| 20 | unsigned long timeout; |
| 21 | |
| 22 | /* Wait max 100 ms */ |
| 23 | timeout = 100; |
| 24 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
| 25 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
| 26 | if (timeout == 0) { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 27 | printf("%s: Reset 0x%x never completed.\n", |
| 28 | __func__, (int)mask); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 29 | return; |
| 30 | } |
| 31 | timeout--; |
| 32 | udelay(1000); |
| 33 | } |
| 34 | } |
| 35 | |
| 36 | static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) |
| 37 | { |
| 38 | int i; |
| 39 | if (cmd->resp_type & MMC_RSP_136) { |
| 40 | /* CRC is stripped so we need to do some shifting. */ |
| 41 | for (i = 0; i < 4; i++) { |
| 42 | cmd->response[i] = sdhci_readl(host, |
| 43 | SDHCI_RESPONSE + (3-i)*4) << 8; |
| 44 | if (i != 3) |
| 45 | cmd->response[i] |= sdhci_readb(host, |
| 46 | SDHCI_RESPONSE + (3-i)*4-1); |
| 47 | } |
| 48 | } else { |
| 49 | cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); |
| 50 | } |
| 51 | } |
| 52 | |
| 53 | static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) |
| 54 | { |
| 55 | int i; |
| 56 | char *offs; |
| 57 | for (i = 0; i < data->blocksize; i += 4) { |
| 58 | offs = data->dest + i; |
| 59 | if (data->flags == MMC_DATA_READ) |
| 60 | *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); |
| 61 | else |
| 62 | sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, |
| 67 | unsigned int start_addr) |
| 68 | { |
Lei Wen | 6c13c66 | 2011-10-08 04:14:57 +0000 | [diff] [blame] | 69 | unsigned int stat, rdy, mask, timeout, block = 0; |
Jaehoon Chung | f77f058 | 2012-09-20 20:31:55 +0000 | [diff] [blame] | 70 | #ifdef CONFIG_MMC_SDMA |
| 71 | unsigned char ctrl; |
Juhyun \(Justin\) Oh | 7d48a73 | 2013-09-13 18:06:00 +0000 | [diff] [blame] | 72 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Jaehoon Chung | f77f058 | 2012-09-20 20:31:55 +0000 | [diff] [blame] | 73 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
Juhyun \(Justin\) Oh | 7d48a73 | 2013-09-13 18:06:00 +0000 | [diff] [blame] | 74 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Jaehoon Chung | f77f058 | 2012-09-20 20:31:55 +0000 | [diff] [blame] | 75 | #endif |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 76 | |
Jaehoon Chung | 30686bd | 2012-09-20 20:31:54 +0000 | [diff] [blame] | 77 | timeout = 1000000; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 78 | rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; |
| 79 | mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; |
| 80 | do { |
| 81 | stat = sdhci_readl(host, SDHCI_INT_STATUS); |
| 82 | if (stat & SDHCI_INT_ERROR) { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 83 | printf("%s: Error detected in status(0x%X)!\n", |
| 84 | __func__, stat); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 85 | return -1; |
| 86 | } |
| 87 | if (stat & rdy) { |
| 88 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) |
| 89 | continue; |
| 90 | sdhci_writel(host, rdy, SDHCI_INT_STATUS); |
| 91 | sdhci_transfer_pio(host, data); |
| 92 | data->dest += data->blocksize; |
| 93 | if (++block >= data->blocks) |
| 94 | break; |
| 95 | } |
| 96 | #ifdef CONFIG_MMC_SDMA |
| 97 | if (stat & SDHCI_INT_DMA_END) { |
| 98 | sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); |
Lei Wen | 8241d40 | 2011-10-08 04:14:58 +0000 | [diff] [blame] | 99 | start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 100 | start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; |
| 101 | sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); |
| 102 | } |
| 103 | #endif |
Lei Wen | 6c13c66 | 2011-10-08 04:14:57 +0000 | [diff] [blame] | 104 | if (timeout-- > 0) |
| 105 | udelay(10); |
| 106 | else { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 107 | printf("%s: Transfer data timeout\n", __func__); |
Lei Wen | 6c13c66 | 2011-10-08 04:14:57 +0000 | [diff] [blame] | 108 | return -1; |
| 109 | } |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 110 | } while (!(stat & SDHCI_INT_DATA_END)); |
| 111 | return 0; |
| 112 | } |
| 113 | |
Przemyslaw Marczak | adccccf | 2013-10-08 18:12:09 +0200 | [diff] [blame] | 114 | /* |
| 115 | * No command will be sent by driver if card is busy, so driver must wait |
| 116 | * for card ready state. |
| 117 | * Every time when card is busy after timeout then (last) timeout value will be |
| 118 | * increased twice but only if it doesn't exceed global defined maximum. |
| 119 | * Each function call will use last timeout value. Max timeout can be redefined |
| 120 | * in board config file. |
| 121 | */ |
| 122 | #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT |
| 123 | #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 |
| 124 | #endif |
| 125 | #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 |
| 126 | |
Jeroen Hofstee | ee54c7b | 2014-10-08 22:57:43 +0200 | [diff] [blame] | 127 | static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 128 | struct mmc_data *data) |
| 129 | { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 130 | struct sdhci_host *host = mmc->priv; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 131 | unsigned int stat = 0; |
| 132 | int ret = 0; |
| 133 | int trans_bytes = 0, is_aligned = 1; |
| 134 | u32 mask, flags, mode; |
Przemyslaw Marczak | adccccf | 2013-10-08 18:12:09 +0200 | [diff] [blame] | 135 | unsigned int time = 0, start_addr = 0; |
Jaehoon Chung | 89237a8 | 2012-04-23 02:36:25 +0000 | [diff] [blame] | 136 | unsigned int retry = 10000; |
Przemyslaw Marczak | adccccf | 2013-10-08 18:12:09 +0200 | [diff] [blame] | 137 | int mmc_dev = mmc->block_dev.dev; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 138 | |
Przemyslaw Marczak | adccccf | 2013-10-08 18:12:09 +0200 | [diff] [blame] | 139 | /* Timeout unit - ms */ |
| 140 | static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 141 | |
| 142 | sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); |
| 143 | mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; |
| 144 | |
| 145 | /* We shouldn't wait for data inihibit for stop commands, even |
| 146 | though they might use busy signaling */ |
| 147 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 148 | mask &= ~SDHCI_DATA_INHIBIT; |
| 149 | |
| 150 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Przemyslaw Marczak | adccccf | 2013-10-08 18:12:09 +0200 | [diff] [blame] | 151 | if (time >= cmd_timeout) { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 152 | printf("%s: MMC: %d busy ", __func__, mmc_dev); |
Przemyslaw Marczak | adccccf | 2013-10-08 18:12:09 +0200 | [diff] [blame] | 153 | if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) { |
| 154 | cmd_timeout += cmd_timeout; |
| 155 | printf("timeout increasing to: %u ms.\n", |
| 156 | cmd_timeout); |
| 157 | } else { |
| 158 | puts("timeout.\n"); |
| 159 | return COMM_ERR; |
| 160 | } |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 161 | } |
Przemyslaw Marczak | adccccf | 2013-10-08 18:12:09 +0200 | [diff] [blame] | 162 | time++; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 163 | udelay(1000); |
| 164 | } |
| 165 | |
| 166 | mask = SDHCI_INT_RESPONSE; |
| 167 | if (!(cmd->resp_type & MMC_RSP_PRESENT)) |
| 168 | flags = SDHCI_CMD_RESP_NONE; |
| 169 | else if (cmd->resp_type & MMC_RSP_136) |
| 170 | flags = SDHCI_CMD_RESP_LONG; |
| 171 | else if (cmd->resp_type & MMC_RSP_BUSY) { |
| 172 | flags = SDHCI_CMD_RESP_SHORT_BUSY; |
| 173 | mask |= SDHCI_INT_DATA_END; |
| 174 | } else |
| 175 | flags = SDHCI_CMD_RESP_SHORT; |
| 176 | |
| 177 | if (cmd->resp_type & MMC_RSP_CRC) |
| 178 | flags |= SDHCI_CMD_CRC; |
| 179 | if (cmd->resp_type & MMC_RSP_OPCODE) |
| 180 | flags |= SDHCI_CMD_INDEX; |
| 181 | if (data) |
| 182 | flags |= SDHCI_CMD_DATA; |
| 183 | |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 184 | /* Set Transfer mode regarding to data flag */ |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 185 | if (data != 0) { |
| 186 | sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); |
| 187 | mode = SDHCI_TRNS_BLK_CNT_EN; |
| 188 | trans_bytes = data->blocks * data->blocksize; |
| 189 | if (data->blocks > 1) |
| 190 | mode |= SDHCI_TRNS_MULTI; |
| 191 | |
| 192 | if (data->flags == MMC_DATA_READ) |
| 193 | mode |= SDHCI_TRNS_READ; |
| 194 | |
| 195 | #ifdef CONFIG_MMC_SDMA |
| 196 | if (data->flags == MMC_DATA_READ) |
| 197 | start_addr = (unsigned int)data->dest; |
| 198 | else |
| 199 | start_addr = (unsigned int)data->src; |
| 200 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && |
| 201 | (start_addr & 0x7) != 0x0) { |
| 202 | is_aligned = 0; |
| 203 | start_addr = (unsigned int)aligned_buffer; |
| 204 | if (data->flags != MMC_DATA_READ) |
| 205 | memcpy(aligned_buffer, data->src, trans_bytes); |
| 206 | } |
| 207 | |
| 208 | sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); |
| 209 | mode |= SDHCI_TRNS_DMA; |
| 210 | #endif |
| 211 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, |
| 212 | data->blocksize), |
| 213 | SDHCI_BLOCK_SIZE); |
| 214 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
| 215 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
| 216 | } |
| 217 | |
| 218 | sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); |
| 219 | #ifdef CONFIG_MMC_SDMA |
Lei Wen | 5b30be0 | 2011-10-08 04:14:54 +0000 | [diff] [blame] | 220 | flush_cache(start_addr, trans_bytes); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 221 | #endif |
| 222 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); |
| 223 | do { |
| 224 | stat = sdhci_readl(host, SDHCI_INT_STATUS); |
| 225 | if (stat & SDHCI_INT_ERROR) |
| 226 | break; |
Jaehoon Chung | 89237a8 | 2012-04-23 02:36:25 +0000 | [diff] [blame] | 227 | if (--retry == 0) |
| 228 | break; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 229 | } while ((stat & mask) != mask); |
| 230 | |
Jaehoon Chung | 89237a8 | 2012-04-23 02:36:25 +0000 | [diff] [blame] | 231 | if (retry == 0) { |
| 232 | if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) |
| 233 | return 0; |
| 234 | else { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 235 | printf("%s: Timeout for status update!\n", __func__); |
Jaehoon Chung | 89237a8 | 2012-04-23 02:36:25 +0000 | [diff] [blame] | 236 | return TIMEOUT; |
| 237 | } |
| 238 | } |
| 239 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 240 | if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { |
| 241 | sdhci_cmd_done(host, cmd); |
| 242 | sdhci_writel(host, mask, SDHCI_INT_STATUS); |
| 243 | } else |
| 244 | ret = -1; |
| 245 | |
| 246 | if (!ret && data) |
| 247 | ret = sdhci_transfer_data(host, data, start_addr); |
| 248 | |
Tushar Behera | 0fba4c2 | 2012-09-20 20:31:57 +0000 | [diff] [blame] | 249 | if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) |
| 250 | udelay(1000); |
| 251 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 252 | stat = sdhci_readl(host, SDHCI_INT_STATUS); |
| 253 | sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); |
| 254 | if (!ret) { |
| 255 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && |
| 256 | !is_aligned && (data->flags == MMC_DATA_READ)) |
| 257 | memcpy(data->dest, aligned_buffer, trans_bytes); |
| 258 | return 0; |
| 259 | } |
| 260 | |
| 261 | sdhci_reset(host, SDHCI_RESET_CMD); |
| 262 | sdhci_reset(host, SDHCI_RESET_DATA); |
| 263 | if (stat & SDHCI_INT_TIMEOUT) |
| 264 | return TIMEOUT; |
| 265 | else |
| 266 | return COMM_ERR; |
| 267 | } |
| 268 | |
| 269 | static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) |
| 270 | { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 271 | struct sdhci_host *host = mmc->priv; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 272 | unsigned int div, clk, timeout; |
| 273 | |
| 274 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
| 275 | |
| 276 | if (clock == 0) |
| 277 | return 0; |
| 278 | |
Jaehoon Chung | 46e627c | 2013-07-19 17:44:49 +0900 | [diff] [blame] | 279 | if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 280 | /* Version 3.00 divisors must be a multiple of 2. */ |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 281 | if (mmc->cfg->f_max <= clock) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 282 | div = 1; |
| 283 | else { |
| 284 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 285 | if ((mmc->cfg->f_max / div) <= clock) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 286 | break; |
| 287 | } |
| 288 | } |
| 289 | } else { |
| 290 | /* Version 2.00 divisors must be a power of 2. */ |
| 291 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 292 | if ((mmc->cfg->f_max / div) <= clock) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 293 | break; |
| 294 | } |
| 295 | } |
| 296 | div >>= 1; |
| 297 | |
Jaehoon Chung | b1929ea | 2012-08-30 16:24:11 +0000 | [diff] [blame] | 298 | if (host->set_clock) |
| 299 | host->set_clock(host->index, div); |
| 300 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 301 | clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
| 302 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
| 303 | << SDHCI_DIVIDER_HI_SHIFT; |
| 304 | clk |= SDHCI_CLOCK_INT_EN; |
| 305 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 306 | |
| 307 | /* Wait max 20 ms */ |
| 308 | timeout = 20; |
| 309 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
| 310 | & SDHCI_CLOCK_INT_STABLE)) { |
| 311 | if (timeout == 0) { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 312 | printf("%s: Internal clock never stabilised.\n", |
| 313 | __func__); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 314 | return -1; |
| 315 | } |
| 316 | timeout--; |
| 317 | udelay(1000); |
| 318 | } |
| 319 | |
| 320 | clk |= SDHCI_CLOCK_CARD_EN; |
| 321 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
| 326 | { |
| 327 | u8 pwr = 0; |
| 328 | |
| 329 | if (power != (unsigned short)-1) { |
| 330 | switch (1 << power) { |
| 331 | case MMC_VDD_165_195: |
| 332 | pwr = SDHCI_POWER_180; |
| 333 | break; |
| 334 | case MMC_VDD_29_30: |
| 335 | case MMC_VDD_30_31: |
| 336 | pwr = SDHCI_POWER_300; |
| 337 | break; |
| 338 | case MMC_VDD_32_33: |
| 339 | case MMC_VDD_33_34: |
| 340 | pwr = SDHCI_POWER_330; |
| 341 | break; |
| 342 | } |
| 343 | } |
| 344 | |
| 345 | if (pwr == 0) { |
| 346 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
| 347 | return; |
| 348 | } |
| 349 | |
Mela Custodio | 8e634a9 | 2012-11-03 17:40:16 +0000 | [diff] [blame] | 350 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
| 351 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 352 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 353 | pwr |= SDHCI_POWER_ON; |
| 354 | |
| 355 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 356 | } |
| 357 | |
Jeroen Hofstee | ee54c7b | 2014-10-08 22:57:43 +0200 | [diff] [blame] | 358 | static void sdhci_set_ios(struct mmc *mmc) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 359 | { |
| 360 | u32 ctrl; |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 361 | struct sdhci_host *host = mmc->priv; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 362 | |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 363 | if (host->set_control_reg) |
| 364 | host->set_control_reg(host); |
| 365 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 366 | if (mmc->clock != host->clock) |
| 367 | sdhci_set_clock(mmc, mmc->clock); |
| 368 | |
| 369 | /* Set bus width */ |
| 370 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| 371 | if (mmc->bus_width == 8) { |
| 372 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
Jaehoon Chung | 46e627c | 2013-07-19 17:44:49 +0900 | [diff] [blame] | 373 | if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || |
| 374 | (host->quirks & SDHCI_QUIRK_USE_WIDE8)) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 375 | ctrl |= SDHCI_CTRL_8BITBUS; |
| 376 | } else { |
Matt Reimer | 9651f59 | 2015-02-19 11:22:53 -0700 | [diff] [blame] | 377 | if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || |
| 378 | (host->quirks & SDHCI_QUIRK_USE_WIDE8)) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 379 | ctrl &= ~SDHCI_CTRL_8BITBUS; |
| 380 | if (mmc->bus_width == 4) |
| 381 | ctrl |= SDHCI_CTRL_4BITBUS; |
| 382 | else |
| 383 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 384 | } |
| 385 | |
| 386 | if (mmc->clock > 26000000) |
| 387 | ctrl |= SDHCI_CTRL_HISPD; |
| 388 | else |
| 389 | ctrl &= ~SDHCI_CTRL_HISPD; |
| 390 | |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 391 | if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) |
| 392 | ctrl &= ~SDHCI_CTRL_HISPD; |
| 393 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 394 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 395 | } |
| 396 | |
Jeroen Hofstee | ee54c7b | 2014-10-08 22:57:43 +0200 | [diff] [blame] | 397 | static int sdhci_init(struct mmc *mmc) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 398 | { |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 399 | struct sdhci_host *host = mmc->priv; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 400 | |
| 401 | if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { |
| 402 | aligned_buffer = memalign(8, 512*1024); |
| 403 | if (!aligned_buffer) { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 404 | printf("%s: Aligned buffer alloc failed!!!\n", |
| 405 | __func__); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 406 | return -1; |
| 407 | } |
| 408 | } |
| 409 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 410 | sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); |
Joe Hershberger | 456f34a | 2012-08-17 10:18:55 +0000 | [diff] [blame] | 411 | |
| 412 | if (host->quirks & SDHCI_QUIRK_NO_CD) { |
| 413 | unsigned int status; |
| 414 | |
| 415 | sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST, |
| 416 | SDHCI_HOST_CONTROL); |
| 417 | |
| 418 | status = sdhci_readl(host, SDHCI_PRESENT_STATE); |
| 419 | while ((!(status & SDHCI_CARD_PRESENT)) || |
| 420 | (!(status & SDHCI_CARD_STATE_STABLE)) || |
| 421 | (!(status & SDHCI_CARD_DETECT_PIN_LEVEL))) |
| 422 | status = sdhci_readl(host, SDHCI_PRESENT_STATE); |
| 423 | } |
| 424 | |
Łukasz Majewski | d56a52a | 2013-01-11 05:08:54 +0000 | [diff] [blame] | 425 | /* Enable only interrupts served by the SD controller */ |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 426 | sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, |
| 427 | SDHCI_INT_ENABLE); |
Łukasz Majewski | d56a52a | 2013-01-11 05:08:54 +0000 | [diff] [blame] | 428 | /* Mask all sdhci interrupt sources */ |
| 429 | sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 430 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 431 | return 0; |
| 432 | } |
| 433 | |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 434 | |
| 435 | static const struct mmc_ops sdhci_ops = { |
| 436 | .send_cmd = sdhci_send_command, |
| 437 | .set_ios = sdhci_set_ios, |
| 438 | .init = sdhci_init, |
| 439 | }; |
| 440 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 441 | int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) |
| 442 | { |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 443 | unsigned int caps; |
| 444 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 445 | host->cfg.name = host->name; |
| 446 | host->cfg.ops = &sdhci_ops; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 447 | |
| 448 | caps = sdhci_readl(host, SDHCI_CAPABILITIES); |
| 449 | #ifdef CONFIG_MMC_SDMA |
| 450 | if (!(caps & SDHCI_CAN_DO_SDMA)) { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 451 | printf("%s: Your controller doesn't support SDMA!!\n", |
| 452 | __func__); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 453 | return -1; |
| 454 | } |
| 455 | #endif |
| 456 | |
| 457 | if (max_clk) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 458 | host->cfg.f_max = max_clk; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 459 | else { |
Jaehoon Chung | 46e627c | 2013-07-19 17:44:49 +0900 | [diff] [blame] | 460 | if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 461 | host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 462 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 463 | else |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 464 | host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 465 | >> SDHCI_CLOCK_BASE_SHIFT; |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 466 | host->cfg.f_max *= 1000000; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 467 | } |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 468 | if (host->cfg.f_max == 0) { |
Darwin Rambo | 4355813 | 2013-12-19 15:13:25 -0800 | [diff] [blame] | 469 | printf("%s: Hardware doesn't specify base clock frequency\n", |
| 470 | __func__); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 471 | return -1; |
| 472 | } |
| 473 | if (min_clk) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 474 | host->cfg.f_min = min_clk; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 475 | else { |
Jaehoon Chung | 46e627c | 2013-07-19 17:44:49 +0900 | [diff] [blame] | 476 | if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 477 | host->cfg.f_min = host->cfg.f_max / |
| 478 | SDHCI_MAX_DIV_SPEC_300; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 479 | else |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 480 | host->cfg.f_min = host->cfg.f_max / |
| 481 | SDHCI_MAX_DIV_SPEC_200; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 482 | } |
| 483 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 484 | host->cfg.voltages = 0; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 485 | if (caps & SDHCI_CAN_VDD_330) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 486 | host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 487 | if (caps & SDHCI_CAN_VDD_300) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 488 | host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 489 | if (caps & SDHCI_CAN_VDD_180) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 490 | host->cfg.voltages |= MMC_VDD_165_195; |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 491 | |
| 492 | if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 493 | host->cfg.voltages |= host->voltages; |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 494 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 495 | host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; |
Jaehoon Chung | 46e627c | 2013-07-19 17:44:49 +0900 | [diff] [blame] | 496 | if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { |
Jagannadha Sutradharudu Teki | 08706be | 2013-05-21 15:01:36 +0530 | [diff] [blame] | 497 | if (caps & SDHCI_CAN_DO_8BIT) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 498 | host->cfg.host_caps |= MMC_MODE_8BIT; |
Jagannadha Sutradharudu Teki | 08706be | 2013-05-21 15:01:36 +0530 | [diff] [blame] | 499 | } |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 500 | if (host->host_caps) |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 501 | host->cfg.host_caps |= host->host_caps; |
| 502 | |
| 503 | host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 504 | |
| 505 | sdhci_reset(host, SDHCI_RESET_ALL); |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 506 | |
| 507 | host->mmc = mmc_create(&host->cfg, host); |
| 508 | if (host->mmc == NULL) { |
| 509 | printf("%s: mmc create fail!\n", __func__); |
| 510 | return -1; |
| 511 | } |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 512 | |
| 513 | return 0; |
| 514 | } |