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Marek Vasut3066a062017-09-15 21:13:55 +02001/*
2 * SuperH Pin Function Controller Support
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __SH_PFC_H
12#define __SH_PFC_H
13
14#include <linux/stringify.h>
15
16enum {
17 PINMUX_TYPE_NONE,
18 PINMUX_TYPE_FUNCTION,
19 PINMUX_TYPE_GPIO,
20 PINMUX_TYPE_OUTPUT,
21 PINMUX_TYPE_INPUT,
22};
23
24#define SH_PFC_PIN_CFG_INPUT (1 << 0)
25#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
26#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
27#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
28#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
29#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
30#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
31
32struct sh_pfc_pin {
33 u16 pin;
34 u16 enum_id;
35 const char *name;
36 unsigned int configs;
37};
38
39#define SH_PFC_PIN_GROUP(n) \
40 { \
41 .name = #n, \
42 .pins = n##_pins, \
43 .mux = n##_mux, \
44 .nr_pins = ARRAY_SIZE(n##_pins), \
45 }
46
47struct sh_pfc_pin_group {
48 const char *name;
49 const unsigned int *pins;
50 const unsigned int *mux;
51 unsigned int nr_pins;
52};
53
54/*
55 * Using union vin_data saves memory occupied by the VIN data pins.
56 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
57 * in this case.
58 */
59#define VIN_DATA_PIN_GROUP(n, s) \
60 { \
61 .name = #n#s, \
62 .pins = n##_pins.data##s, \
63 .mux = n##_mux.data##s, \
64 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
65 }
66
67union vin_data {
68 unsigned int data24[24];
69 unsigned int data20[20];
70 unsigned int data16[16];
71 unsigned int data12[12];
72 unsigned int data10[10];
73 unsigned int data8[8];
74 unsigned int data4[4];
75};
76
77#define SH_PFC_FUNCTION(n) \
78 { \
79 .name = #n, \
80 .groups = n##_groups, \
81 .nr_groups = ARRAY_SIZE(n##_groups), \
82 }
83
84struct sh_pfc_function {
85 const char *name;
86 const char * const *groups;
87 unsigned int nr_groups;
88};
89
90struct pinmux_func {
91 u16 enum_id;
92 const char *name;
93};
94
95struct pinmux_cfg_reg {
96 u32 reg;
97 u8 reg_width, field_width;
98 const u16 *enum_ids;
99 const u8 *var_field_width;
100};
101
102/*
103 * Describe a config register consisting of several fields of the same width
104 * - name: Register name (unused, for documentation purposes only)
105 * - r: Physical register address
106 * - r_width: Width of the register (in bits)
107 * - f_width: Width of the fixed-width register fields (in bits)
108 * This macro must be followed by initialization data: For each register field
109 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
110 * one for each possible combination of the register field bit values.
111 */
112#define PINMUX_CFG_REG(name, r, r_width, f_width) \
113 .reg = r, .reg_width = r_width, .field_width = f_width, \
114 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
115
116/*
117 * Describe a config register consisting of several fields of different widths
118 * - name: Register name (unused, for documentation purposes only)
119 * - r: Physical register address
120 * - r_width: Width of the register (in bits)
121 * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
122 * From left to right (i.e. MSB to LSB)
123 * This macro must be followed by initialization data: For each register field
124 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
125 * one for each possible combination of the register field bit values.
126 */
127#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
128 .reg = r, .reg_width = r_width, \
129 .var_field_width = (const u8 [r_width]) \
130 { var_fw0, var_fwn, 0 }, \
131 .enum_ids = (const u16 [])
132
133struct pinmux_drive_reg_field {
134 u16 pin;
135 u8 offset;
136 u8 size;
137};
138
139struct pinmux_drive_reg {
140 u32 reg;
141 const struct pinmux_drive_reg_field fields[8];
142};
143
144#define PINMUX_DRIVE_REG(name, r) \
145 .reg = r, \
146 .fields =
147
148struct pinmux_data_reg {
149 u32 reg;
150 u8 reg_width;
151 const u16 *enum_ids;
152};
153
154/*
155 * Describe a data register
156 * - name: Register name (unused, for documentation purposes only)
157 * - r: Physical register address
158 * - r_width: Width of the register (in bits)
159 * This macro must be followed by initialization data: For each register bit
160 * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
161 */
162#define PINMUX_DATA_REG(name, r, r_width) \
163 .reg = r, .reg_width = r_width, \
164 .enum_ids = (const u16 [r_width]) \
165
166struct pinmux_irq {
167 const short *gpios;
168};
169
170/*
171 * Describe the mapping from GPIOs to a single IRQ
172 * - ids...: List of GPIOs that are mapped to the same IRQ
173 */
174#define PINMUX_IRQ(ids...) \
175 { .gpios = (const short []) { ids, -1 } }
176
177struct pinmux_range {
178 u16 begin;
179 u16 end;
180 u16 force;
181};
182
183struct sh_pfc_bias_info {
184 u16 pin;
185 u16 reg : 11;
186 u16 bit : 5;
187};
188
189struct sh_pfc_pin_range;
190
191struct sh_pfc {
192 struct device *dev;
193 const struct sh_pfc_soc_info *info;
194
195 void *regs;
196
197 struct sh_pfc_pin_range *ranges;
198 unsigned int nr_ranges;
199
200 unsigned int nr_gpio_pins;
201
202 struct sh_pfc_chip *gpio;
203};
204
205struct sh_pfc_soc_operations {
206 int (*init)(struct sh_pfc *pfc);
207 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
208 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
209 unsigned int bias);
210 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
211};
212
213struct sh_pfc_soc_info {
214 const char *name;
215 const struct sh_pfc_soc_operations *ops;
216
217 struct pinmux_range input;
218 struct pinmux_range output;
219 struct pinmux_range function;
220
221 const struct sh_pfc_pin *pins;
222 unsigned int nr_pins;
223 const struct sh_pfc_pin_group *groups;
224 unsigned int nr_groups;
225 const struct sh_pfc_function *functions;
226 unsigned int nr_functions;
227
228 const struct pinmux_cfg_reg *cfg_regs;
229 const struct pinmux_drive_reg *drive_regs;
230 const struct pinmux_data_reg *data_regs;
231
232 const u16 *pinmux_data;
233 unsigned int pinmux_data_size;
234
235 const struct pinmux_irq *gpio_irq;
236 unsigned int gpio_irq_size;
237
238 u32 unlock_reg;
239};
240
241u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
242void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);
243const struct sh_pfc_bias_info *
244sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
245 unsigned int num, unsigned int pin);
Marek Vasut489d79c2017-11-26 18:07:29 +0100246int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
Marek Vasut3066a062017-09-15 21:13:55 +0200247
Marek Vasutc40f2d62018-01-17 22:18:59 +0100248extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
Marek Vasut06ef9e82018-01-17 17:14:45 +0100249extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
Marek Vasut1ef39302018-01-17 22:29:50 +0100250extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
Marek Vasut06ef9e82018-01-17 17:14:45 +0100251extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
Marek Vasut4dd88d52018-01-17 22:33:59 +0100252extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
Marek Vasut3066a062017-09-15 21:13:55 +0200253extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
254extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
Marek Vasuta0e11e52017-10-09 20:57:29 +0200255extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
Marek Vasut7d35e642017-10-08 20:57:37 +0200256extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
Marek Vasut3066a062017-09-15 21:13:55 +0200257/* -----------------------------------------------------------------------------
258 * Helper macros to create pin and port lists
259 */
260
261/*
262 * sh_pfc_soc_info pinmux_data array macros
263 */
264
265/*
266 * Describe generic pinmux data
267 * - data_or_mark: *_DATA or *_MARK enum ID
268 * - ids...: List of enum IDs to associate with data_or_mark
269 */
270#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
271
272/*
273 * Describe a pinmux configuration without GPIO function that needs
274 * configuration in a Peripheral Function Select Register (IPSR)
275 * - ipsr: IPSR field (unused, for documentation purposes only)
276 * - fn: Function name, referring to a field in the IPSR
277 */
278#define PINMUX_IPSR_NOGP(ipsr, fn) \
279 PINMUX_DATA(fn##_MARK, FN_##fn)
280
281/*
282 * Describe a pinmux configuration with GPIO function that needs configuration
283 * in both a Peripheral Function Select Register (IPSR) and in a
284 * GPIO/Peripheral Function Select Register (GPSR)
285 * - ipsr: IPSR field
286 * - fn: Function name, also referring to the IPSR field
287 */
288#define PINMUX_IPSR_GPSR(ipsr, fn) \
289 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
290
291/*
292 * Describe a pinmux configuration without GPIO function that needs
293 * configuration in a Peripheral Function Select Register (IPSR), and where the
294 * pinmux function has a representation in a Module Select Register (MOD_SEL).
295 * - ipsr: IPSR field (unused, for documentation purposes only)
296 * - fn: Function name, also referring to the IPSR field
297 * - msel: Module selector
298 */
299#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
300 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
301
302/*
303 * Describe a pinmux configuration with GPIO function where the pinmux function
304 * has no representation in a Peripheral Function Select Register (IPSR), but
305 * instead solely depends on a group selection.
306 * - gpsr: GPSR field
307 * - fn: Function name, also referring to the GPSR field
308 * - gsel: Group selector
309 */
310#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
311 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
312
313/*
314 * Describe a pinmux configuration with GPIO function that needs configuration
315 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
316 * Function Select Register (GPSR), and where the pinmux function has a
317 * representation in a Module Select Register (MOD_SEL).
318 * - ipsr: IPSR field
319 * - fn: Function name, also referring to the IPSR field
320 * - msel: Module selector
321 */
322#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
323 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
324
325/*
326 * Describe a pinmux configuration for a single-function pin with GPIO
327 * capability.
328 * - fn: Function name
329 */
330#define PINMUX_SINGLE(fn) \
331 PINMUX_DATA(fn##_MARK, FN_##fn)
332
333/*
334 * GP port style (32 ports banks)
335 */
336
337#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
338 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
339#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
340
341#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
342 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
343 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
344 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
345 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
346#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
347
Marek Vasuta0e11e52017-10-09 20:57:29 +0200348#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
349 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
350 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
351#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
352
Marek Vasut3066a062017-09-15 21:13:55 +0200353#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
354 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
355 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
356 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
357 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
358 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
359#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
360
361#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
362 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
363 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
364#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
365
366#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
367 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
368 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
369#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
370
371#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
372 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
373 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
374 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
375#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
376
377#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
378 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
379 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
380 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
381#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
382
383#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
384 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
385 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
386#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
387
388#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
389 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
390 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
391#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
392
393#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
394 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
395 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
396#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
397
398#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
399 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
400 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
401#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
402
403#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
404 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
405 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
406 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
407#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
408
409#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
410 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
411 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
412#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
413
Marek Vasuta0e11e52017-10-09 20:57:29 +0200414#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
415 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
416 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
417 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
418#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
419
Marek Vasut3066a062017-09-15 21:13:55 +0200420#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
421 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
422 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
423 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
424#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
425
426#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
427 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
428 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
429#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
430
431#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
432 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
433 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
434 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
435#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
436
437#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
438 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
439 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
440 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
441#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
442
443#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
444 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
445 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
446#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
447
448#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
449 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
450 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
451#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
452
453#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
454 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
455 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
456 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
457#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
458
459#define PORT_GP_32_REV(bank, fn, sfx) \
460 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
461 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
462 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
463 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
464 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
465 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
466 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
467 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
468 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
469 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
470 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
471 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
472 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
473 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
474 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
475 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
476
477/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
478#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
479#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
480
481/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
482#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
483 { \
484 .pin = (bank * 32) + _pin, \
485 .name = __stringify(_name), \
486 .enum_id = _name##_DATA, \
487 .configs = cfg, \
488 }
489#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
490
491/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
492#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
493#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
494
495/*
496 * PORT style (linear pin space)
497 */
498
499#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
500
501#define PORT_10(pn, fn, pfx, sfx) \
502 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
503 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
504 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
505 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
506 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
507
508#define PORT_90(pn, fn, pfx, sfx) \
509 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
510 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
511 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
512 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
513 PORT_10(pn+90, fn, pfx##9, sfx)
514
515/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
516#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
517#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
518
519/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
520#define PINMUX_GPIO(_pin) \
521 [GPIO_##_pin] = { \
522 .pin = (u16)-1, \
523 .name = __stringify(GPIO_##_pin), \
524 .enum_id = _pin##_DATA, \
525 }
526
527/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
528#define SH_PFC_PIN_CFG(_pin, cfgs) \
529 { \
530 .pin = _pin, \
531 .name = __stringify(PORT##_pin), \
532 .enum_id = PORT##_pin##_DATA, \
533 .configs = cfgs, \
534 }
535
536/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
537#define SH_PFC_PIN_NAMED(row, col, _name) \
538 { \
539 .pin = PIN_NUMBER(row, col), \
540 .name = __stringify(PIN_##_name), \
541 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
542 }
543
544/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
545#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
546 { \
547 .pin = PIN_NUMBER(row, col), \
548 .name = __stringify(PIN_##_name), \
549 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
550 }
551
552/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
553 * PORT_name_OUT, PORT_name_IN marks
554 */
555#define _PORT_DATA(pn, pfx, sfx) \
556 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
557 PORT##pfx##_OUT, PORT##pfx##_IN)
558#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
559
560/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
561#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
562 [gpio - (base)] = { \
563 .name = __stringify(gpio), \
564 .enum_id = data_or_mark, \
565 }
566#define GPIO_FN(str) \
567 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
568
569/*
570 * PORTnCR helper macro for SH-Mobile/R-Mobile
571 */
572#define PORTCR(nr, reg) \
573 { \
574 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
575 /* PULMD[1:0], handled by .set_bias() */ \
576 0, 0, 0, 0, \
577 /* IE and OE */ \
578 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
579 /* SEC, not supported */ \
580 0, 0, \
581 /* PTMD[2:0] */ \
582 PORT##nr##_FN0, PORT##nr##_FN1, \
583 PORT##nr##_FN2, PORT##nr##_FN3, \
584 PORT##nr##_FN4, PORT##nr##_FN5, \
585 PORT##nr##_FN6, PORT##nr##_FN7 \
586 } \
587 }
588
589/*
590 * GPIO number helper macro for R-Car
591 */
592#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
593
594#endif /* __SH_PFC_H */