Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004 Freescale Semiconductor. |
| 3 | * |
| 4 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
| 26 | #include <pci.h> |
| 27 | #include <asm/processor.h> |
| 28 | #include <asm/immap_85xx.h> |
| 29 | #include <spd.h> |
Andy Fleming | 239e75f | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 30 | #include <miiphy.h> |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 31 | |
| 32 | #include "../common/cadmus.h" |
| 33 | #include "../common/eeprom.h" |
Matthew McClintock | aa6dd06 | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 34 | #include "../common/via.h" |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 35 | |
| 36 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 37 | extern void ddr_enable_ecc(unsigned int dram_size); |
| 38 | #endif |
| 39 | |
| 40 | extern long int spd_sdram(void); |
| 41 | |
| 42 | void local_bus_init(void); |
| 43 | void sdram_init(void); |
| 44 | |
| 45 | int board_early_init_f (void) |
| 46 | { |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | int checkboard (void) |
| 51 | { |
| 52 | volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; |
| 53 | volatile ccsr_gur_t *gur = &immap->im_gur; |
Zang Roy-r61911 | 9bc0b27 | 2006-12-15 14:43:31 +0800 | [diff] [blame] | 54 | volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 55 | |
| 56 | /* PCI slot in USER bits CSR[6:7] by convention. */ |
| 57 | uint pci_slot = get_pci_slot (); |
| 58 | |
| 59 | uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ |
| 60 | uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ |
| 61 | uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ |
| 62 | uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ |
| 63 | |
| 64 | uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ |
| 65 | |
| 66 | uint cpu_board_rev = get_cpu_board_revision (); |
| 67 | |
| 68 | printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", |
| 69 | get_board_version (), pci_slot); |
| 70 | |
| 71 | printf ("CPU Board Revision %d.%d (0x%04x)\n", |
| 72 | MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), |
| 73 | MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); |
| 74 | |
| 75 | printf (" PCI1: %d bit, %s MHz, %s\n", |
| 76 | (pci1_32) ? 32 : 64, |
| 77 | (pci1_speed == 33000000) ? "33" : |
| 78 | (pci1_speed == 66000000) ? "66" : "unknown", |
| 79 | pci1_clk_sel ? "sync" : "async"); |
| 80 | |
| 81 | if (pci_dual) { |
| 82 | printf (" PCI2: 32 bit, 66 MHz, %s\n", |
| 83 | pci2_clk_sel ? "sync" : "async"); |
| 84 | } else { |
| 85 | printf (" PCI2: disabled\n"); |
| 86 | } |
| 87 | |
| 88 | /* |
| 89 | * Initialize local bus. |
| 90 | */ |
| 91 | local_bus_init (); |
| 92 | |
Zang Roy-r61911 | 9bc0b27 | 2006-12-15 14:43:31 +0800 | [diff] [blame] | 93 | /* |
| 94 | * Fix CPU2 errata: A core hang possible while executing a |
| 95 | * msync instruction and a snoopable transaction from an I/O |
| 96 | * master tagged to make quick forward progress is present. |
| 97 | */ |
| 98 | ecm->eebpcr |= (1 << 16); |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 99 | |
| 100 | /* |
| 101 | * Hack TSEC 3 and 4 IO voltages. |
| 102 | */ |
| 103 | gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | long int |
| 109 | initdram(int board_type) |
| 110 | { |
| 111 | long dram_size = 0; |
| 112 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 113 | |
| 114 | puts("Initializing\n"); |
| 115 | |
| 116 | #if defined(CONFIG_DDR_DLL) |
| 117 | { |
| 118 | /* |
| 119 | * Work around to stabilize DDR DLL MSYNC_IN. |
| 120 | * Errata DDR9 seems to have been fixed. |
| 121 | * This is now the workaround for Errata DDR11: |
| 122 | * Override DLL = 1, Course Adj = 1, Tap Select = 0 |
| 123 | */ |
| 124 | |
| 125 | volatile ccsr_gur_t *gur= &immap->im_gur; |
| 126 | |
| 127 | gur->ddrdllcr = 0x81000000; |
| 128 | asm("sync;isync;msync"); |
| 129 | udelay(200); |
| 130 | } |
| 131 | #endif |
| 132 | dram_size = spd_sdram(); |
| 133 | |
| 134 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 135 | /* |
| 136 | * Initialize and enable DDR ECC. |
| 137 | */ |
| 138 | ddr_enable_ecc(dram_size); |
| 139 | #endif |
| 140 | /* |
| 141 | * SDRAM Initialization |
| 142 | */ |
| 143 | sdram_init(); |
| 144 | |
| 145 | puts(" DDR: "); |
| 146 | return dram_size; |
| 147 | } |
| 148 | |
| 149 | /* |
| 150 | * Initialize Local Bus |
| 151 | */ |
| 152 | void |
| 153 | local_bus_init(void) |
| 154 | { |
| 155 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 156 | volatile ccsr_gur_t *gur = &immap->im_gur; |
| 157 | volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
| 158 | |
| 159 | uint clkdiv; |
| 160 | uint lbc_hz; |
| 161 | sys_info_t sysinfo; |
| 162 | |
| 163 | get_sys_info(&sysinfo); |
| 164 | clkdiv = (lbc->lcrr & 0x0f) * 2; |
| 165 | lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
| 166 | |
| 167 | gur->lbiuiplldcr1 = 0x00078080; |
| 168 | if (clkdiv == 16) { |
| 169 | gur->lbiuiplldcr0 = 0x7c0f1bf0; |
| 170 | } else if (clkdiv == 8) { |
| 171 | gur->lbiuiplldcr0 = 0x6c0f1bf0; |
| 172 | } else if (clkdiv == 4) { |
| 173 | gur->lbiuiplldcr0 = 0x5c0f1bf0; |
| 174 | } |
| 175 | |
| 176 | lbc->lcrr |= 0x00030000; |
| 177 | |
| 178 | asm("sync;isync;msync"); |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * Initialize SDRAM memory on the Local Bus. |
| 183 | */ |
| 184 | void |
| 185 | sdram_init(void) |
| 186 | { |
| 187 | #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) |
| 188 | |
| 189 | uint idx; |
| 190 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 191 | volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
| 192 | uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
| 193 | uint cpu_board_rev; |
| 194 | uint lsdmr_common; |
| 195 | |
| 196 | puts(" SDRAM: "); |
| 197 | |
| 198 | print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
| 199 | |
| 200 | /* |
| 201 | * Setup SDRAM Base and Option Registers |
| 202 | */ |
| 203 | lbc->or2 = CFG_OR2_PRELIM; |
| 204 | asm("msync"); |
| 205 | |
| 206 | lbc->br2 = CFG_BR2_PRELIM; |
| 207 | asm("msync"); |
| 208 | |
| 209 | lbc->lbcr = CFG_LBC_LBCR; |
| 210 | asm("msync"); |
| 211 | |
| 212 | |
| 213 | lbc->lsrt = CFG_LBC_LSRT; |
| 214 | lbc->mrtpr = CFG_LBC_MRTPR; |
| 215 | asm("msync"); |
| 216 | |
| 217 | /* |
| 218 | * MPC8548 uses "new" 15-16 style addressing. |
| 219 | */ |
| 220 | cpu_board_rev = get_cpu_board_revision(); |
| 221 | lsdmr_common = CFG_LBC_LSDMR_COMMON; |
| 222 | lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; |
| 223 | |
| 224 | /* |
| 225 | * Issue PRECHARGE ALL command. |
| 226 | */ |
| 227 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; |
| 228 | asm("sync;msync"); |
| 229 | *sdram_addr = 0xff; |
| 230 | ppcDcbf((unsigned long) sdram_addr); |
| 231 | udelay(100); |
| 232 | |
| 233 | /* |
| 234 | * Issue 8 AUTO REFRESH commands. |
| 235 | */ |
| 236 | for (idx = 0; idx < 8; idx++) { |
| 237 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; |
| 238 | asm("sync;msync"); |
| 239 | *sdram_addr = 0xff; |
| 240 | ppcDcbf((unsigned long) sdram_addr); |
| 241 | udelay(100); |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * Issue 8 MODE-set command. |
| 246 | */ |
| 247 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; |
| 248 | asm("sync;msync"); |
| 249 | *sdram_addr = 0xff; |
| 250 | ppcDcbf((unsigned long) sdram_addr); |
| 251 | udelay(100); |
| 252 | |
| 253 | /* |
| 254 | * Issue NORMAL OP command. |
| 255 | */ |
| 256 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; |
| 257 | asm("sync;msync"); |
| 258 | *sdram_addr = 0xff; |
| 259 | ppcDcbf((unsigned long) sdram_addr); |
| 260 | udelay(200); /* Overkill. Must wait > 200 bus cycles */ |
| 261 | |
| 262 | #endif /* enable SDRAM init */ |
| 263 | } |
| 264 | |
| 265 | #if defined(CFG_DRAM_TEST) |
| 266 | int |
| 267 | testdram(void) |
| 268 | { |
| 269 | uint *pstart = (uint *) CFG_MEMTEST_START; |
| 270 | uint *pend = (uint *) CFG_MEMTEST_END; |
| 271 | uint *p; |
| 272 | |
| 273 | printf("Testing DRAM from 0x%08x to 0x%08x\n", |
| 274 | CFG_MEMTEST_START, |
| 275 | CFG_MEMTEST_END); |
| 276 | |
| 277 | printf("DRAM test phase 1:\n"); |
| 278 | for (p = pstart; p < pend; p++) |
| 279 | *p = 0xaaaaaaaa; |
| 280 | |
| 281 | for (p = pstart; p < pend; p++) { |
| 282 | if (*p != 0xaaaaaaaa) { |
| 283 | printf ("DRAM test fails at: %08x\n", (uint) p); |
| 284 | return 1; |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | printf("DRAM test phase 2:\n"); |
| 289 | for (p = pstart; p < pend; p++) |
| 290 | *p = 0x55555555; |
| 291 | |
| 292 | for (p = pstart; p < pend; p++) { |
| 293 | if (*p != 0x55555555) { |
| 294 | printf ("DRAM test fails at: %08x\n", (uint) p); |
| 295 | return 1; |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | printf("DRAM test passed.\n"); |
| 300 | return 0; |
| 301 | } |
| 302 | #endif |
| 303 | |
| 304 | #if defined(CONFIG_PCI) |
Matthew McClintock | aa6dd06 | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 305 | /* For some reason the Tundra PCI bridge shows up on itself as a |
| 306 | * different device. Work around that by refusing to configure it. |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 307 | */ |
Matthew McClintock | aa6dd06 | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 308 | void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 309 | |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 310 | static struct pci_config_table pci_mpc85xxcds_config_table[] = { |
Matthew McClintock | aa6dd06 | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 311 | {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, |
| 312 | {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, |
| 313 | {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, |
| 314 | {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, |
| 315 | {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, |
| 316 | {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, |
| 317 | {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 318 | }; |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 319 | |
Matthew McClintock | aa6dd06 | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 320 | static struct pci_controller hose[] = { |
| 321 | { config_table: pci_mpc85xxcds_config_table,}, |
| 322 | #ifdef CONFIG_MPC85XX_PCI2 |
| 323 | {}, |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 324 | #endif |
| 325 | }; |
| 326 | |
| 327 | #endif /* CONFIG_PCI */ |
| 328 | |
| 329 | void |
| 330 | pci_init_board(void) |
| 331 | { |
| 332 | #ifdef CONFIG_PCI |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 333 | pci_mpc85xx_init(&hose); |
| 334 | #endif |
| 335 | } |
Andy Fleming | 239e75f | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 336 | |
| 337 | int last_stage_init(void) |
| 338 | { |
Jon Loeliger | 249688a | 2006-10-20 15:54:34 -0500 | [diff] [blame] | 339 | unsigned short temp; |
Andy Fleming | 239e75f | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 340 | |
| 341 | /* Change the resistors for the PHY */ |
| 342 | /* This is needed to get the RGMII working for the 1.3+ |
| 343 | * CDS cards */ |
| 344 | if (get_board_version() == 0x13) { |
| 345 | miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, |
| 346 | TSEC1_PHY_ADDR, 29, 18); |
| 347 | |
| 348 | miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, |
| 349 | TSEC1_PHY_ADDR, 30, &temp); |
| 350 | |
| 351 | temp = (temp & 0xf03f); |
| 352 | temp |= 2 << 9; /* 36 ohm */ |
| 353 | temp |= 2 << 6; /* 39 ohm */ |
| 354 | |
| 355 | miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, |
| 356 | TSEC1_PHY_ADDR, 30, temp); |
| 357 | |
| 358 | miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, |
| 359 | TSEC1_PHY_ADDR, 29, 3); |
| 360 | |
| 361 | miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, |
| 362 | TSEC1_PHY_ADDR, 30, 0x8000); |
| 363 | } |
| 364 | |
| 365 | return 0; |
| 366 | } |