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git01.mediatek.com / filogic / uboot / 714e7e3b250288a19e3882f184deccb0df875ad6 / . / arch / arm / dts / imx7ulp.dtsi
blob: 494b9d98b2a4baf1579dc78c054852be0aeb1a10 [file] [log] [blame]
Peng Fanadaf8be2017-02-22 16:21:54 +0800[diff] [blame]1/*
2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
Gaurav Jain714e7e32022-03-24 11:50:31 +0530[diff] [blame^]3 * Copyright 2021 NXP
Peng Fanadaf8be2017-02-22 16:21:54 +0800[diff] [blame]4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <dt-bindings/clock/imx7ulp-clock.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/gpio/gpio.h>
13#include "skeleton.dtsi"
14#include "imx7ulp-pinfunc.h"
15
16/ {
17 interrupt-parent = <&intc>;
18
19 aliases {
Fabio Estevam8764dff2019-11-05 09:47:54 -0300[diff] [blame]20 gpio0 = &gpio4;
21 gpio1 = &gpio5;
22 gpio2 = &gpio0;
23 gpio3 = &gpio1;
24 gpio4 = &gpio2;
25 gpio5 = &gpio3;
Peng Fanadaf8be2017-02-22 16:21:54 +0800[diff] [blame]26 mmc0 = &usdhc0;
27 mmc1 = &usdhc1;
28 serial0 = &lpuart4;
29 serial1 = &lpuart5;
30 serial2 = &lpuart6;
31 serial3 = &lpuart7;
32 usbphy0 = &usbphy1;
Fabio Estevam8764dff2019-11-05 09:47:54 -0300[diff] [blame]33 usb0 = &usbotg1;
Peng Fan18a912d2018-01-02 15:41:53 +0800[diff] [blame]34 i2c4 = &lpi2c4;
35 i2c5 = &lpi2c5;
36 i2c6 = &lpi2c6;
37 i2c7 = &lpi2c7;
Fabio Estevam8764dff2019-11-05 09:47:54 -0300[diff] [blame]38 spi0 = &qspi1;
Peng Fanadaf8be2017-02-22 16:21:54 +0800[diff] [blame]39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 cpu0: cpu@0 {
46 compatible = "arm,cortex-a7";
47 device_type = "cpu";
48 reg = <0>;
49 };
50 };
51
52 reserved-memory {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 /* global autoconfigured region for contiguous allocations */
58 linux,cma {
59 compatible = "shared-dma-pool";
60 reusable;
61 size = <0xC000000>;
62 alignment = <0x2000>;
63 linux,cma-default;
64 };
65
66 rpmsg_reserved: rpmsg@9FFF0000 {
67 no-map;
68 reg = <0x9FF00000 0x100000>;
69 };
70
71 };
72
73 intc: interrupt-controller@40021000 {
74 compatible = "arm,cortex-a7-gic";
75 #interrupt-cells = <3>;
76 interrupt-controller;
77 reg = <0x40021000 0x1000>,
78 <0x40022000 0x100>;
79 };
80
81 clocks {
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 ckil: clock@0 {
86 compatible = "fixed-clock";
87 #clock-cells = <0>;
88 clock-frequency = <32768>;
89 clock-output-names = "ckil";
90 };
91
92 osc: clock@1 {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <24000000>;
96 clock-output-names = "osc";
97 };
98
99 sirc: clock@2 {
100 compatible = "fixed-clock";
101 #clock-cells = <0>;
102 clock-frequency = <16000000>;
103 clock-output-names = "sirc";
104 };
105
106 firc: clock@3 {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <48000000>;
110 clock-output-names = "firc";
111 };
112
113 upll: clock@4 {
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <480000000>;
117 clock-output-names = "upll";
118 };
119
120 mpll: clock@5 {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <480000000>;
124 clock-output-names = "mpll";
125 };
126 };
127
128 sram: sram@20000000 {
129 compatible = "fsl,lpm-sram";
130 reg = <0x1fffc000 0x4000>;
131 };
132
133 ahbbridge0: ahb-bridge0@40000000 {
134 compatible = "fsl,aips-bus", "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 reg = <0x40000000 0x800000>;
138 ranges;
139
140 edma0: dma-controller@40080000 {
141 #dma-cells = <2>;
142 compatible = "nxp,imx7ulp-edma";
143 reg = <0x40080000 0x2000>,
144 <0x40210000 0x1000>;
145 dma-channels = <32>;
146 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
163 clock-names = "dma", "dmamux0";
164 clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
165 };
166
167 mu: mu@40220000 {
168 compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu";
169 reg = <0x40220000 0x1000>;
170 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
172 status = "okay";
173 };
174
175 nmi: nmi@40220000 {
176 compatible = "fsl,imx7ulp-nmi";
177 reg = <0x40220000 0x1000>;
178 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
179 status = "okay";
180 };
181
182 rpmsg: rpmsg{
183 compatible = "fsl,imx7ulp-rpmsg";
184 memory-region = <&rpmsg_reserved>;
185 status = "disabled";
186 };
187
188 snvs: snvs@40230000 {
189 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
190 reg = <0x40230000 0x10000>;
191
192 snvs_rtc: snvs-rtc-lp{
193 compatible = "fsl,sec-v4.0-mon-rtc-lp";
194 regmap =<&snvs>;
195 offset = <0x34>;
196 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
197 clock-names = "snvs-rtc";
198 clocks = <&clks IMX7ULP_CLK_SNVS>;
199 };
200 };
201
Gaurav Jain714e7e32022-03-24 11:50:31 +0530[diff] [blame^]202 crypto: crypto@40240000 {
203 compatible = "fsl,sec-v4.0";
204 #address-cells = <1>;
205 #size-cells = <1>;
206 reg = <0x40240000 0x10000>;
207 ranges = <0 0x40240000 0x10000>;
208 clocks = <&clks IMX7ULP_CLK_CAAM>,
209 <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
210 clock-names = "aclk", "ipg";
211
212 sec_jr0: jr@1000 {
213 compatible = "fsl,sec-v4.0-job-ring";
214 reg = <0x1000 0x1000>;
215 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
216 };
217
218 sec_jr1: jr@2000 {
219 compatible = "fsl,sec-v4.0-job-ring";
220 reg = <0x2000 0x1000>;
221 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
222 };
223 };
224
Peng Fanadaf8be2017-02-22 16:21:54 +0800[diff] [blame]225 tpm5: tpm@40260000 {
226 compatible = "fsl,imx7ulp-tpm";
227 reg = <0x40260000 0x1000>;
228 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&clks IMX7ULP_CLK_LPTPM5>;
230 };
231
232 lpit: 1@40270000 {
233 compatible = "fsl,imx-lpit";
234 reg = <0x40270000 0x1000>;
235 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
236 /* clocks = <&lpclk>;*/
237 clocks = <&clks IMX7ULP_CLK_LPIT1>;
238 assigned-clock-rates = <48000000>;
239 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
240 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
241 };
242
243 lpi2c4: lpi2c4@402B0000 {
244 compatible = "fsl,imx7ulp-lpi2c";
245 reg = <0x402B0000 0x10000>;
246 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clks IMX7ULP_CLK_LPI2C4>;
248 clock-names = "ipg";
249 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
250 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
251 assigned-clock-rates = <48000000>;
252 status = "disabled";
253 };
254
255 lpi2c5: lpi2c4@402C0000 {
256 compatible = "fsl,imx7ulp-lpi2c";
257 reg = <0x402C0000 0x10000>;
258 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clks IMX7ULP_CLK_LPI2C5>;
260 clock-names = "ipg";
261 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
262 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
263 assigned-clock-rates = <48000000>;
264 status = "disabled";
265 };
266
267 lpspi2: lpspi@40290000 {
268 compatible = "fsl,imx7ulp-spi";
269 reg = <0x40290000 0x10000>;
270 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clks IMX7ULP_CLK_LPSPI2>;
272 clock-names = "ipg";
273 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
274 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
275 assigned-clock-rates = <48000000>;
276 status = "disabled";
277 };
278
279 lpspi3: lpspi@402A0000 {
280 compatible = "fsl,imx7ulp-spi";
281 reg = <0x402A0000 0x10000>;
282 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clks IMX7ULP_CLK_LPSPI3>;
284 clock-names = "ipg";
285 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
286 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
287 assigned-clock-rates = <48000000>;
288 status = "disabled";
289 };
290
291 lpuart4: serial@402D0000 {
292 compatible = "fsl,imx7ulp-lpuart";
293 reg = <0x402D0000 0x1000>;
294 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks IMX7ULP_CLK_LPUART4>;
296 clock-names = "ipg";
297 assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
298 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
299 assigned-clock-rates = <24000000>;
300 status = "disabled";
301 };
302
303 lpuart5: serial@402E0000 {
304 compatible = "fsl,imx7ulp-lpuart";
305 reg = <0x402E0000 0x1000>;
306 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&clks IMX7ULP_CLK_LPUART5>;
308 clock-names = "ipg";
309 assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
310 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
311 assigned-clock-rates = <48000000>;
312 dmas = <&edma0 0 20>, <&edma0 0 19>;
313 dma-names = "tx","rx";
314 status = "disabled";
315 };
316
317 usbotg1: usb@40330000 {
318 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb",
319 "fsl,imx27-usb";
320 reg = <0x40330000 0x200>;
321 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clks IMX7ULP_CLK_USB0>;
323 fsl,usbphy = <&usbphy1>;
324 fsl,usbmisc = <&usbmisc1 0>;
325 ahb-burst-config = <0x0>;
326 tx-burst-size-dword = <0x8>;
327 rx-burst-size-dword = <0x8>;
328 status = "disabled";
329 };
330
331 usbmisc1: usbmisc@40330200 {
332 #index-cells = <1>;
333 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
334 "fsl,imx6q-usbmisc";
335 reg = <0x40330200 0x200>;
336 };
337
338 usbphy1: usbphy@0x40350000 {
339 compatible = "fsl,imx7ulp-usbphy",
340 "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
341 reg = <0x40350000 0x1000>;
342 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clks IMX7ULP_CLK_USB_PHY>;
344 nxp,sim = <&sim>;
345 };
346
347 usdhc0: usdhc@40370000 {
348 compatible = "fsl,imx7ulp-usdhc";
349 reg = <0x40370000 0x10000>;
350 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
352 <&clks IMX7ULP_CLK_NIC1_DIV>,
353 <&clks IMX7ULP_CLK_USDHC0>;
354 clock-names ="ipg", "ahb", "per";
355 bus-width = <4>;
356 fsl,tuning-start-tap = <20>;
357 fsl,tuning-step= <2>;
358 status = "disabled";
359 };
360
361 usdhc1: usdhc@40380000 {
362 compatible = "fsl,imx7ulp-usdhc";
363 reg = <0x40380000 0x10000>;
364 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
366 <&clks IMX7ULP_CLK_NIC1_DIV>,
367 <&clks IMX7ULP_CLK_USDHC1>;
368 clock-names ="ipg", "ahb", "per";
369 bus-width = <4>;
370 fsl,tuning-start-tap = <20>;
371 fsl,tuning-step= <2>;
372 status = "disabled";
373 };
374
375 wdog1: wdog@403D0000 {
376 compatible = "fsl,imx7ulp-wdt";
377 reg = <0x403D0000 0x10000>;
378 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX7ULP_CLK_WDG1>;
380 assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
381 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
382 /*
383 * As the 1KHz LPO clock rate is not trimed,the actually clock
384 * is about 667Hz, so the init timeout 60s should set 40*1000
385 * in the TOVAL register.
386 */
387 timeout-sec = <40>;
388 };
389
390 wdog2: wdog@40430000 {
391 compatible = "fsl,imx7ulp-wdt";
392 reg = <0x40430000 0x10000>;
393 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks IMX7ULP_CLK_WDG2>;
395 assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
396 assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
397 timeout-sec = <40>;
398 };
399
400 clks: scg1@403E0000 {
401 compatible = "fsl,imx7ulp-scg1";
402 reg = <0x403E0000 0x10000>;
403 clocks = <&ckil>, <&osc>, <&sirc>,
404 <&firc>, <&upll>, <&mpll>;
405 clock-names = "ckil", "osc", "sirc",
406 "firc", "upll", "mpll";
407 #clock-cells = <1>;
408 assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
409 <&clks IMX7ULP_CLK_USDHC1>;
410 assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
411 <&clks IMX7ULP_CLK_NIC1_DIV>;
412 };
413
414 pcc2: pcc2@403F0000 {
415 compatible = "fsl,imx7ulp-pcc2";
416 reg = <0x403F0000 0x10000>;
417 };
418
419 pmc1: pmc1@40400000 {
420 compatible = "fsl,imx7ulp-pmc1";
421 reg = <0x40400000 0x1000>;
422 };
423
424 smc1: smc1@40410000 {
425 compatible = "fsl,imx7ulp-smc1";
426 reg = <0x40410000 0x1000>;
427 };
428
429 };
430
431 ahbbridge1: ahb-bridge1@40800000 {
432 compatible = "fsl,aips-bus", "simple-bus";
433 #address-cells = <1>;
434 #size-cells = <1>;
435 reg = <0x40800000 0x800000>;
436 ranges;
437
438 lpi2c6: lpi2c6@40A40000 {
439 compatible = "fsl,imx7ulp-lpi2c";
440 reg = <0x40A40000 0x10000>;
441 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clks IMX7ULP_CLK_LPI2C6>;
443 clock-names = "ipg";
444 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
445 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
446 assigned-clock-rates = <48000000>;
447 status = "disabled";
448 };
449
450 lpi2c7: lpi2c7@40A50000 {
451 compatible = "fsl,imx7ulp-lpi2c";
452 reg = <0x40A50000 0x10000>;
453 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&clks IMX7ULP_CLK_LPI2C7>;
455 clock-names = "ipg";
456 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
457 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
458 assigned-clock-rates = <48000000>;
459 status = "disabled";
460 };
461
462 lpuart6: serial@40A60000 {
463 compatible = "fsl,imx7ulp-lpuart";
464 reg = <0x40A60000 0x1000>;
465 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clks IMX7ULP_CLK_LPUART6>;
467 clock-names = "ipg";
468 assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
469 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
470 assigned-clock-rates = <48000000>;
471 dmas = <&edma0 0 22>, <&edma0 0 21>;
472 dma-names = "tx","rx";
473 status = "disabled";
474 };
475
476 lpuart7: serial@40A70000 {
477 compatible = "fsl,imx7ulp-lpuart";
478 reg = <0x40A70000 0x1000>;
479 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&clks IMX7ULP_CLK_LPUART7>;
481 clock-names = "ipg";
482 assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
483 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
484 assigned-clock-rates = <50000000>;
485 dmas = <&edma0 0 24>, <&edma0 0 23>;
486 dma-names = "tx","rx";
487 status = "disabled";
488 };
489
490 lcdif: lcdif@40AA0000 {
491 compatible = "fsl,imx7ulp-lcdif";
492 reg = <0x40aa0000 0x10000>;
493 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clks IMX7ULP_CLK_DUMMY>,
495 <&clks IMX7ULP_CLK_LCDIF>,
496 <&clks IMX7ULP_CLK_DUMMY>;
497 clock-names = "axi", "pix", "disp_axi";
498 status = "disabled";
499 };
500
501 mipi_dsi: mipi_dsi@40A90000 {
502 compatible = "fsl,imx7ulp-mipi-dsi";
503 reg = <0x40A90000 0x10000>;
504 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clks IMX7ULP_CLK_DSI>;
506 clock-names = "mipi_dsi_clk";
507 sim = <&sim>;
508 status = "disabled";
509 };
510
511 mmdc: mmdc@40ab0000 {
512 compatible = "fsl,imx7ulp-mmdc";
513 reg = <0x40ab0000 0x4000>;
514 };
515
516 pcc3: pcc3@40B30000 {
517 compatible = "fsl,imx7ulp-pcc3";
518 reg = <0x40B30000 0x10000>;
519 };
520
521 iomuxc: iomuxc@4103D000 {
522 compatible = "fsl,imx7ulp-iomuxc-0";
523 reg = <0x4103D000 0x1000>;
524 fsl,mux_mask = <0xf00>;
525 status = "disabled";
526 };
527
528 iomuxc1: iomuxc1@40ac0000 {
529 compatible = "fsl,imx7ulp-iomuxc-1";
530 reg = <0x40ac0000 0x1000>;
531 fsl,mux_mask = <0xf00>;
532 };
533
Fabio Estevam8764dff2019-11-05 09:47:54 -0300[diff] [blame]534 gpio4: gpio@4103f000 {
535 compatible = "fsl,imx7ulp-gpio";
536 reg = <0x4103f000 0x1000 0x4100F000 0x40>;
537 gpio-controller;
538 #gpio-cells = <2>;
539 gpio-ranges = <&iomuxc 0 0 32>;
540 };
541
542 gpio5: gpio@41040000 {
543 compatible = "fsl,imx7ulp-gpio";
544 reg = <0x41040000 0x1000 0x4100F040 0x40>;
545 gpio-controller;
546 #gpio-cells = <2>;
547 gpio-ranges = <&iomuxc 0 32 32>;
548 };
549
Peng Fanadaf8be2017-02-22 16:21:54 +0800[diff] [blame]550 gpio0: gpio@40ae0000 {
551 compatible = "fsl,imx7ulp-gpio";
552 reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
553 gpio-controller;
554 #gpio-cells = <2>;
555 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
556 interrupt-controller;
557 #interrupt-cells = <2>;
558 gpio-ranges = <&iomuxc1 0 0 32>;
559 };
560
561 gpio1: gpio@40af0000 {
562 compatible = "fsl,imx7ulp-gpio";
563 reg = <0x40af0000 0x1000 0x400F0040 0x40>;
564 gpio-controller;
565 #gpio-cells = <2>;
566 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-controller;
568 #interrupt-cells = <2>;
569 gpio-ranges = <&iomuxc1 0 32 32>;
570 };
571
572 gpio2: gpio@40b00000 {
573 compatible = "fsl,imx7ulp-gpio";
574 reg = <0x40b00000 0x1000 0x400F0080 0x40>;
575 gpio-controller;
576 #gpio-cells = <2>;
577 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
580 gpio-ranges = <&iomuxc1 0 64 32>;
581 };
582
583 gpio3: gpio@40b10000 {
584 compatible = "fsl,imx7ulp-gpio";
585 reg = <0x40b10000 0x1000 0x400F00c0 0x40>;
586 gpio-controller;
587 #gpio-cells = <2>;
588 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
591 gpio-ranges = <&iomuxc1 0 96 32>;
592 };
593
594 pmc0: pmc0@410a1000 {
595 compatible = "fsl,imx7ulp-pmc0";
596 reg = <0x410a1000 0x1000>;
597 };
598
599 sim: sim@410a3000 {
600 compatible = "fsl,imx7ulp-sim", "syscon";
601 reg = <0x410a3000 0x1000>;
602 };
603
604 qspi1: qspi@410A5000 {
605 #address-cells = <1>;
606 #size-cells = <0>;
607 compatible = "fsl,imx7ulp-qspi";
608 reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>;
609 reg-names = "QuadSPI", "QuadSPI-memory";
610 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&clks IMX7ULP_CLK_DUMMY>,
612 <&clks IMX7ULP_CLK_DUMMY>;
613 clock-names = "qspi_en", "qspi";
614 status = "disabled";
615 };
616
617 gpu: gpu@41800000 {
618 compatible = "fsl,imx6q-gpu";
619 reg = <0x41800000 0x80000>, <0x41880000 0x80000>,
620 <0x60000000 0x40000000>, <0x0 0x4000000>;
621 reg-names = "iobase_3d", "iobase_2d",
622 "phys_baseaddr", "contiguous_mem";
623 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-names = "irq_3d", "irq_2d";
626 clocks = <&clks IMX7ULP_CLK_GPU3D>,
627 <&clks IMX7ULP_CLK_NIC1_DIV>,
628 <&clks IMX7ULP_CLK_GPU_DIV>,
629 <&clks IMX7ULP_CLK_GPU2D>,
630 <&clks IMX7ULP_CLK_NIC1_DIV>,
631 <&clks IMX7ULP_CLK_NIC1_DIV>;
632 clock-names = "gpu3d_clk", "gpu3d_shader_clk",
633 "gpu3d_axi_clk", "gpu2d_clk",
634 "gpu2d_shader_clk", "gpu2d_axi_clk";
635 };
636 };
637
638 imx_ion {
639 compatible = "fsl,mxc-ion";
640 fsl,heap-id = <0>;
641 };
642};