blob: 1205e8597d9a94c1e95cf56987536c8549f9ecae [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Phil Sutterd76eba62015-12-25 14:41:25 +01002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Phil Sutterd76eba62015-12-25 14:41:25 +01004 */
5
6#ifndef _CONFIG_SYNOLOGY_DS414_H
7#define _CONFIG_SYNOLOGY_DS414_H
8
Phil Sutteref534b22021-03-07 22:22:27 +01009/* Vendor kernel expects this MACH_TYPE */
10#define CONFIG_MACH_TYPE 3036
11
Phil Sutterd76eba62015-12-25 14:41:25 +010012/*
13 * High Level Configuration Options (easy to change)
14 */
Phil Sutterd76eba62015-12-25 14:41:25 +010015
16/*
17 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
18 * for DDR ECC byte filling in the SPL before loading the main
19 * U-Boot into it.
20 */
Phil Sutterd76eba62015-12-25 14:41:25 +010021
Phil Sutterd76eba62015-12-25 14:41:25 +010022/* I2C */
Phil Sutterd76eba62015-12-25 14:41:25 +010023#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
24#define CONFIG_SYS_I2C_SLAVE 0x0
25#define CONFIG_SYS_I2C_SPEED 100000
26
Phil Sutterd76eba62015-12-25 14:41:25 +010027/* PCIe support */
28#ifndef CONFIG_SPL_BUILD
Phil Sutterd76eba62015-12-25 14:41:25 +010029#define CONFIG_PCI_SCAN_SHOW
30#endif
31
32/* USB/EHCI/XHCI configuration */
Phil Sutterd76eba62015-12-25 14:41:25 +010033#define CONFIG_EHCI_IS_TDI
Phil Sutterd76eba62015-12-25 14:41:25 +010034
35/*
36 * mv-common.h should be defined after CMD configs since it used them
37 * to enable certain macros
38 */
39#include "mv-common.h"
40
41/*
42 * Memory layout while starting into the bin_hdr via the
43 * BootROM:
44 *
45 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
46 * 0x4000.4030 bin_hdr start address
47 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
48 * 0x4007.fffc BootROM stack top
49 *
50 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
51 * L2 cache thus cannot be used.
52 */
53
54/* SPL */
55/* Defines for SPL */
Phil Sutterd76eba62015-12-25 14:41:25 +010056#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
57
58#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
59#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
60
61#ifdef CONFIG_SPL_BUILD
62#define CONFIG_SYS_MALLOC_SIMPLE
63#endif
64
65#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
66#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
67
Phil Sutterd76eba62015-12-25 14:41:25 +010068/* DS414 bus width is 32bits */
69#define CONFIG_DDR_32BIT
70
Phil Sutterd76eba62015-12-25 14:41:25 +010071/* Default Environment */
Phil Sutterd76eba62015-12-25 14:41:25 +010072#define CONFIG_LOADADDR 0x80000
Phil Sutteref534b22021-03-07 22:22:27 +010073#define CONFIG_BOOTCOMMAND \
74 "sf probe; " \
75 "sf read ${loadaddr} 0xd0000 0x2d0000; " \
76 "sf read ${ramdisk_addr_r} 0x3a0000 0x430000; " \
77 "bootm ${loadaddr} ${ramdisk_addr_r}"
78
79#define CONFIG_EXTRA_ENV_SETTINGS \
80 "initrd_high=0xffffffff\0" \
81 "ramdisk_addr_r=0x8000000\0" \
82 "usb0Mode=host\0usb1Mode=host\0usb2Mode=device\0" \
Phil Sutter6d1bcbf2021-03-05 21:05:45 +010083 "ethmtu=1500\0eth1mtu=1500\0" \
84 "update_uboot=sf probe; dhcp; " \
85 "mw.b ${loadaddr} 0x0 0xd0000; " \
86 "tftpboot ${loadaddr} u-boot-spl.kwb; " \
87 "sf update ${loadaddr} 0x0 0xd0000\0"
88
Phil Sutterd76eba62015-12-25 14:41:25 +010089
Phil Sutter246a61f2021-01-03 23:06:44 +010090/* increase autoneg timeout, my NIC sucks */
91#define PHY_ANEG_TIMEOUT 16000
92
Phil Sutterd76eba62015-12-25 14:41:25 +010093#endif /* _CONFIG_SYNOLOGY_DS414_H */