Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 2 | /* |
Stefan Roese | 114bba6 | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 3 | * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _CONFIG_DB_MV7846MP_GP_H |
| 7 | #define _CONFIG_DB_MV7846MP_GP_H |
| 8 | |
| 9 | /* |
| 10 | * High Level Configuration Options (easy to change) |
| 11 | */ |
Stefan Roese | f3679a3 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 12 | #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ |
| 13 | |
Stefan Roese | 3dbf35c | 2015-08-06 14:27:36 +0200 | [diff] [blame] | 14 | /* |
| 15 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
| 16 | * for DDR ECC byte filling in the SPL before loading the main |
| 17 | * U-Boot into it. |
| 18 | */ |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 19 | |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 20 | /* I2C */ |
Paul Kocialkowski | 2fae3e7 | 2015-04-10 23:09:51 +0200 | [diff] [blame] | 21 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 22 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
| 23 | #define CONFIG_SYS_I2C_SPEED 100000 |
| 24 | |
Stefan Roese | 58613c7 | 2015-07-22 18:05:43 +0200 | [diff] [blame] | 25 | /* USB/EHCI configuration */ |
Stefan Roese | 58613c7 | 2015-07-22 18:05:43 +0200 | [diff] [blame] | 26 | #define CONFIG_EHCI_IS_TDI |
Anton Schubert | 11b8ebf | 2015-07-23 15:02:09 +0200 | [diff] [blame] | 27 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
Stefan Roese | 58613c7 | 2015-07-22 18:05:43 +0200 | [diff] [blame] | 28 | |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 29 | /* Environment in SPI NOR flash */ |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 30 | |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 31 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 32 | |
Anton Schubert | 3ceae9e | 2015-07-15 14:50:05 +0200 | [diff] [blame] | 33 | /* SATA support */ |
Stefan Roese | 114bba6 | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 34 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
Stefan Roese | 114bba6 | 2015-12-03 12:39:45 +0100 | [diff] [blame] | 35 | #define CONFIG_LBA48 |
Anton Schubert | 3ceae9e | 2015-07-15 14:50:05 +0200 | [diff] [blame] | 36 | |
Stefan Roese | 7d86529 | 2015-08-11 09:36:15 +0200 | [diff] [blame] | 37 | /* PCIe support */ |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 38 | #ifndef CONFIG_SPL_BUILD |
Stefan Roese | 7d86529 | 2015-08-11 09:36:15 +0200 | [diff] [blame] | 39 | #define CONFIG_PCI_SCAN_SHOW |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 40 | #endif |
Stefan Roese | 7d86529 | 2015-08-11 09:36:15 +0200 | [diff] [blame] | 41 | |
Stefan Roese | 645949b | 2015-07-23 10:26:18 +0200 | [diff] [blame] | 42 | /* NAND */ |
Stefan Roese | 645949b | 2015-07-23 10:26:18 +0200 | [diff] [blame] | 43 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 44 | |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 45 | /* |
| 46 | * mv-common.h should be defined after CMD configs since it used them |
| 47 | * to enable certain macros |
| 48 | */ |
| 49 | #include "mv-common.h" |
| 50 | |
Stefan Roese | f3679a3 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 51 | /* |
| 52 | * Memory layout while starting into the bin_hdr via the |
| 53 | * BootROM: |
| 54 | * |
| 55 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) |
| 56 | * 0x4000.4030 bin_hdr start address |
| 57 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) |
| 58 | * 0x4007.fffc BootROM stack top |
| 59 | * |
| 60 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in |
| 61 | * L2 cache thus cannot be used. |
| 62 | */ |
| 63 | |
| 64 | /* SPL */ |
| 65 | /* Defines for SPL */ |
Stefan Roese | f3679a3 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 66 | #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) |
| 67 | |
| 68 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) |
| 69 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
| 70 | |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 71 | #ifdef CONFIG_SPL_BUILD |
| 72 | #define CONFIG_SYS_MALLOC_SIMPLE |
| 73 | #endif |
Stefan Roese | f3679a3 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 74 | |
| 75 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) |
| 76 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
| 77 | |
Stefan Roese | f3679a3 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 78 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ |
Stefan Roese | f3679a3 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 79 | #define CONFIG_SPD_EEPROM 0x4e |
Stefan Roese | ff7ad17 | 2015-12-10 15:02:38 +0100 | [diff] [blame] | 80 | #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ |
Stefan Roese | f3679a3 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 81 | |
Stefan Roese | 0391577 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 82 | #endif /* _CONFIG_DB_MV7846MP_GP_H */ |