Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: BSD-3-Clause |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Clock drivers for Qualcomm APQ8096 |
| 4 | * |
| 5 | * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org> |
| 6 | * |
| 7 | * Based on Little Kernel driver, simplified |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <clk-uclass.h> |
| 12 | #include <dm.h> |
| 13 | #include <errno.h> |
| 14 | #include <asm/io.h> |
| 15 | #include <linux/bitops.h> |
Caleb Connolly | 42f4aff | 2024-02-26 17:26:39 +0000 | [diff] [blame] | 16 | #include <dt-bindings/clock/qcom,gcc-msm8996.h> |
Caleb Connolly | 878b26a | 2023-11-07 12:40:59 +0000 | [diff] [blame] | 17 | |
| 18 | #include "clock-qcom.h" |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 19 | |
Caleb Connolly | 10a0abb | 2023-11-07 12:41:03 +0000 | [diff] [blame] | 20 | /* Clocks: (from CLK_CTL_BASE) */ |
| 21 | #define GPLL0_STATUS (0x0000) |
| 22 | #define APCS_GPLL_ENA_VOTE (0x52000) |
| 23 | #define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) |
| 24 | |
| 25 | #define SDCC2_BCR (0x14000) /* block reset */ |
| 26 | #define SDCC2_APPS_CBCR (0x14004) /* branch control */ |
| 27 | #define SDCC2_AHB_CBCR (0x14008) |
| 28 | #define SDCC2_CMD_RCGR (0x14010) |
| 29 | #define SDCC2_CFG_RCGR (0x14014) |
| 30 | #define SDCC2_M (0x14018) |
| 31 | #define SDCC2_N (0x1401C) |
| 32 | #define SDCC2_D (0x14020) |
| 33 | |
| 34 | #define BLSP2_AHB_CBCR (0x25004) |
| 35 | #define BLSP2_UART2_APPS_CBCR (0x29004) |
| 36 | #define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) |
| 37 | #define BLSP2_UART2_APPS_CFG_RCGR (0x29010) |
| 38 | #define BLSP2_UART2_APPS_M (0x29014) |
| 39 | #define BLSP2_UART2_APPS_N (0x29018) |
| 40 | #define BLSP2_UART2_APPS_D (0x2901C) |
| 41 | |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 42 | /* GPLL0 clock control registers */ |
| 43 | #define GPLL0_STATUS_ACTIVE BIT(30) |
| 44 | #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) |
| 45 | |
| 46 | static const struct bcr_regs sdc_regs = { |
| 47 | .cfg_rcgr = SDCC2_CFG_RCGR, |
| 48 | .cmd_rcgr = SDCC2_CMD_RCGR, |
| 49 | .M = SDCC2_M, |
| 50 | .N = SDCC2_N, |
| 51 | .D = SDCC2_D, |
| 52 | }; |
| 53 | |
Ramon Fried | ae29977 | 2018-05-16 12:13:39 +0300 | [diff] [blame] | 54 | static const struct pll_vote_clk gpll0_vote_clk = { |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 55 | .status = GPLL0_STATUS, |
| 56 | .status_bit = GPLL0_STATUS_ACTIVE, |
| 57 | .ena_vote = APCS_GPLL_ENA_VOTE, |
| 58 | .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, |
| 59 | }; |
| 60 | |
Ramon Fried | ed09eef | 2019-01-12 11:47:24 +0200 | [diff] [blame] | 61 | static struct vote_clk gcc_blsp2_ahb_clk = { |
| 62 | .cbcr_reg = BLSP2_AHB_CBCR, |
| 63 | .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 64 | .vote_bit = BIT(15), |
| 65 | }; |
| 66 | |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 67 | static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) |
| 68 | { |
Caleb Connolly | 397c84f | 2023-11-07 12:41:05 +0000 | [diff] [blame] | 69 | int div = 5; |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 70 | |
| 71 | clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); |
| 72 | clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, |
Caleb Connolly | fbacc67 | 2023-11-07 12:41:04 +0000 | [diff] [blame] | 73 | CFG_CLK_SRC_GPLL0, 8); |
Ramon Fried | ae29977 | 2018-05-16 12:13:39 +0300 | [diff] [blame] | 74 | clk_enable_gpll0(priv->base, &gpll0_vote_clk); |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 75 | clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); |
| 76 | |
| 77 | return rate; |
| 78 | } |
| 79 | |
Ramon Fried | ed09eef | 2019-01-12 11:47:24 +0200 | [diff] [blame] | 80 | static const struct bcr_regs uart2_regs = { |
| 81 | .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR, |
| 82 | .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR, |
| 83 | .M = BLSP2_UART2_APPS_M, |
| 84 | .N = BLSP2_UART2_APPS_N, |
| 85 | .D = BLSP2_UART2_APPS_D, |
| 86 | }; |
| 87 | |
| 88 | static int clk_init_uart(struct msm_clk_priv *priv) |
| 89 | { |
| 90 | /* Enable AHB clock */ |
| 91 | clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); |
| 92 | |
| 93 | /* 7372800 uart block clock @ GPLL0 */ |
| 94 | clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, |
Caleb Connolly | fbacc67 | 2023-11-07 12:41:04 +0000 | [diff] [blame] | 95 | CFG_CLK_SRC_GPLL0, 16); |
Ramon Fried | ed09eef | 2019-01-12 11:47:24 +0200 | [diff] [blame] | 96 | |
| 97 | /* Vote for gpll0 clock */ |
| 98 | clk_enable_gpll0(priv->base, &gpll0_vote_clk); |
| 99 | |
| 100 | /* Enable core clk */ |
| 101 | clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR); |
| 102 | |
| 103 | return 0; |
| 104 | } |
| 105 | |
Caleb Connolly | 10a0abb | 2023-11-07 12:41:03 +0000 | [diff] [blame] | 106 | static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 107 | { |
| 108 | struct msm_clk_priv *priv = dev_get_priv(clk->dev); |
| 109 | |
| 110 | switch (clk->id) { |
Caleb Connolly | 42f4aff | 2024-02-26 17:26:39 +0000 | [diff] [blame] | 111 | case GCC_SDCC1_APPS_CLK: /* SDC1 */ |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 112 | return clk_init_sdc(priv, rate); |
| 113 | break; |
Caleb Connolly | 42f4aff | 2024-02-26 17:26:39 +0000 | [diff] [blame] | 114 | case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ |
Ramon Fried | ed09eef | 2019-01-12 11:47:24 +0200 | [diff] [blame] | 115 | return clk_init_uart(priv); |
Jorge Ramirez-Ortiz | 9f2d1b2 | 2018-01-10 11:33:50 +0100 | [diff] [blame] | 116 | default: |
| 117 | return 0; |
| 118 | } |
| 119 | } |
Sumit Garg | 1d1ca6e | 2022-08-04 19:57:14 +0530 | [diff] [blame] | 120 | |
Caleb Connolly | 10a0abb | 2023-11-07 12:41:03 +0000 | [diff] [blame] | 121 | static struct msm_clk_data apq8096_clk_data = { |
| 122 | .set_rate = apq8096_clk_set_rate, |
| 123 | }; |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 124 | |
| 125 | static const struct udevice_id gcc_apq8096_of_match[] = { |
| 126 | { |
Caleb Connolly | 3e88e6e | 2024-02-26 17:26:09 +0000 | [diff] [blame] | 127 | .compatible = "qcom,gcc-msm8996", |
Caleb Connolly | 10a0abb | 2023-11-07 12:41:03 +0000 | [diff] [blame] | 128 | .data = (ulong)&apq8096_clk_data, |
Konrad Dybcio | 6c0b844 | 2023-11-07 12:41:01 +0000 | [diff] [blame] | 129 | }, |
| 130 | { } |
| 131 | }; |
| 132 | |
| 133 | U_BOOT_DRIVER(gcc_apq8096) = { |
| 134 | .name = "gcc_apq8096", |
| 135 | .id = UCLASS_NOP, |
| 136 | .of_match = gcc_apq8096_of_match, |
| 137 | .bind = qcom_cc_bind, |
| 138 | .flags = DM_FLAG_PRE_RELOC, |
| 139 | }; |