Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Allied Telesis Labs |
| 4 | */ |
| 5 | |
| 6 | #ifndef _CONFIG_X530_H |
| 7 | #define _CONFIG_X530_H |
| 8 | |
| 9 | /* |
| 10 | * High Level Configuration Options (easy to change) |
| 11 | */ |
| 12 | |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 13 | /* |
| 14 | * NS16550 Configuration |
| 15 | */ |
| 16 | #define CONFIG_SYS_NS16550_SERIAL |
| 17 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK |
| 18 | #if !defined(CONFIG_DM_SERIAL) |
| 19 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 20 | #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE |
| 21 | #endif |
| 22 | |
| 23 | /* |
| 24 | * Serial Port configuration |
| 25 | * The following definitions let you select what serial you want to use |
| 26 | * for your console driver. |
| 27 | */ |
| 28 | |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 29 | /* NAND */ |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 30 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 31 | |
| 32 | #define BBT_CUSTOM_SCAN |
| 33 | #define BBT_CUSTOM_SCAN_PAGE 0 |
| 34 | #define BBT_CUSTOM_SCAN_POSITION 2048 |
| 35 | |
| 36 | /* SPI NOR flash default params, used by sf commands */ |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 37 | |
| 38 | #define MTDIDS_DEFAULT "nand0=nand" |
| 39 | #define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" |
| 40 | #define MTDPARTS_MTDOOPS "errlog" |
| 41 | |
| 42 | /* Partition support */ |
| 43 | |
| 44 | /* Additional FS support/configuration */ |
| 45 | |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 46 | /* Environment in SPI NOR flash */ |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 47 | |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 48 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
| 49 | |
| 50 | /* PCIe support */ |
| 51 | #ifndef CONFIG_SPL_BUILD |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 52 | #define CONFIG_PCI_SCAN_SHOW |
| 53 | #endif |
| 54 | |
| 55 | /* NAND */ |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 56 | |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 57 | #include <asm/arch/config.h> |
| 58 | |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 59 | /* Keep device tree and initrd in low memory so the kernel can access them */ |
| 60 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 61 | "fdt_high=0x10000000\0" \ |
| 62 | "initrd_high=0x10000000\0" |
| 63 | |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 64 | #define CONFIG_UBI_PART user |
| 65 | #define CONFIG_UBIFS_VOLUME user |
| 66 | |
| 67 | /* SPL */ |
| 68 | |
| 69 | /* Defines for SPL */ |
| 70 | #define CONFIG_SPL_SIZE (140 << 10) |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 71 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) |
| 72 | |
| 73 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) |
| 74 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
| 75 | |
| 76 | #ifdef CONFIG_SPL_BUILD |
| 77 | #define CONFIG_SYS_MALLOC_SIMPLE |
| 78 | #endif |
| 79 | |
| 80 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) |
| 81 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
| 82 | |
Chris Packham | b55b2c9 | 2019-01-10 21:01:00 +1300 | [diff] [blame] | 83 | #endif /* _CONFIG_X530_H */ |