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git01.mediatek.com / filogic / uboot / 70f3a2e944b3249da69cddaa5879c6248896eaac / . / include / configs / ethernut5.h
blob: c0bdfd3f8f1438bbb01e342b052d1eff07b80d3c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]2/*
3 * (C) Copyright 2011
4 * egnite GmbH <info@egnite.de>
5 *
6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/hardware.h>
13
14/* The first stage boot loader expects u-boot running at this address. */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]15
16/* The first stage boot loader takes care of low level initialization. */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]17
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]18/* CPU information */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]19
20/* ARM asynchronous clock */
21#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
22#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]23
24/* 32kB internal SRAM */
25#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
26#define CONFIG_SRAM_SIZE (32 << 10)
Rob Herring72e6d652012-07-13 09:44:01 +0000[diff] [blame]27#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
28 GENERATED_GBL_DATA_SIZE)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]29
30/* 128MB SDRAM in 1 bank */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]31#define CONFIG_SYS_SDRAM_BASE 0x20000000
32#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]33
34/* 512kB on-chip NOR flash */
35# define CONFIG_SYS_MAX_FLASH_BANKS 1
36# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
37# define CONFIG_AT91_EFLASH
38# define CONFIG_SYS_MAX_FLASH_SECT 32
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]39# define CONFIG_EFLASH_PROTSECTORS 1
40
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]41
Wenyou.Yang@microchip.comc99bfb42017-07-21 14:30:57 +0800[diff] [blame]42/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]43
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]44/* NAND flash */
45#ifdef CONFIG_CMD_NAND
46#define CONFIG_SYS_MAX_NAND_DEVICE 1
47#define CONFIG_SYS_NAND_BASE 0x40000000
48#define CONFIG_SYS_NAND_DBW_8
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]49/* our ALE is AD21 */
50#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
51/* our CLE is AD22 */
52#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmanna4c24d32013-11-29 12:13:45 +0100[diff] [blame]53#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]54#endif
55
56/* JFFS2 */
57#ifdef CONFIG_CMD_JFFS2
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]58#define CONFIG_JFFS2_NAND
59#endif
60
61/* Ethernet */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]62#define CONFIG_NET_RETRY_COUNT 20
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]63#define CONFIG_RMII
64#define CONFIG_PHY_ID 0
65#define CONFIG_MACB_SEARCH_PHY
66
67/* MMC */
68#ifdef CONFIG_CMD_MMC
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]69#define CONFIG_GENERIC_ATMEL_MCI
70#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
71#endif
72
73/* USB */
74#ifdef CONFIG_CMD_USB
75#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +0800[diff] [blame]76#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]77#define CONFIG_USB_OHCI_NEW
78#define CONFIG_SYS_USB_OHCI_CPU_INIT
79#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
80#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
81#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]82#endif
83
84/* RTC */
85#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]86#define CONFIG_SYS_I2C_RTC_ADDR 0x51
87#endif
88
89/* I2C */
90#define CONFIG_SYS_MAX_I2C_BUS 1
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100[diff] [blame]91
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]92#define I2C_SOFT_DECLARATIONS
93
94#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
95#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
96
97#define I2C_INIT { \
98 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
99 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
100 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
101 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
102 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
103}
104
105#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
106#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
107#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
108#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
109#define I2C_DELAY udelay(100)
110#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
111
112/* DHCP/BOOTP options */
113#ifdef CONFIG_CMD_DHCP
114#define CONFIG_BOOTP_BOOTFILESIZE
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]115#define CONFIG_SYS_AUTOLOAD "n"
116#endif
117
118/* File systems */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]119
120/* Boot command */
Wenyou.Yang@microchip.comc99bfb42017-07-21 14:30:57 +0800[diff] [blame]121#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
122 "sf read 0x22000000 0xc6000 0x294000; " \
123 "bootm 0x22000000"
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]124
125/* Misc. u-boot settings */
Tim Schendekehl024b61c2011-11-01 23:55:01 +0000[diff] [blame]126
127#endif