blob: 5120c7b3777008897d980598db8b53aec5555f30 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Dirk Eibachfb605942017-02-22 16:07:23 +01002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
Dirk Eibachfb605942017-02-22 16:07:23 +01005 */
6
7#ifndef _CONFIG_CONTROLCENTERDC_H
8#define _CONFIG_CONTROLCENTERDC_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
13#define CONFIG_CUSTOMER_BOARD_SUPPORT
14
Dirk Eibachfb605942017-02-22 16:07:23 +010015/*
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
18 * U-Boot into it.
19 */
Dirk Eibachfb605942017-02-22 16:07:23 +010020
Dirk Eibachfb605942017-02-22 16:07:23 +010021/*
Dirk Eibachfb605942017-02-22 16:07:23 +010022 * SATA/SCSI/AHCI configuration
23 */
Dirk Eibachfb605942017-02-22 16:07:23 +010024#define CONFIG_SCSI_AHCI_PLAT
25#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
26#define CONFIG_SYS_SCSI_MAX_LUN 1
27#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
28 CONFIG_SYS_SCSI_MAX_LUN)
29
Dirk Eibachfb605942017-02-22 16:07:23 +010030/* Environment in SPI NOR flash */
Dirk Eibachfb605942017-02-22 16:07:23 +010031
Dirk Eibachfb605942017-02-22 16:07:23 +010032#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
33
34/* PCIe support */
35#ifndef CONFIG_SPL_BUILD
Dirk Eibachfb605942017-02-22 16:07:23 +010036#define CONFIG_PCI_SCAN_SHOW
37#endif
38
Dirk Eibachfb605942017-02-22 16:07:23 +010039/*
40 * Software (bit-bang) MII driver configuration
41 */
Dirk Eibachfb605942017-02-22 16:07:23 +010042#define CONFIG_BITBANGMII_MULTI
43
44/* SPL */
45/*
46 * Select the boot device here
47 *
48 * Currently supported are:
49 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
50 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
51 */
52#define SPL_BOOT_SPI_NOR_FLASH 1
53#define SPL_BOOT_SDIO_MMC_CARD 2
54#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
55
56/* Defines for SPL */
Dirk Eibachfb605942017-02-22 16:07:23 +010057#define CONFIG_SPL_SIZE (160 << 10)
58
59#if defined(CONFIG_SECURED_MODE_IMAGE)
Dirk Eibachfb605942017-02-22 16:07:23 +010060#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614)
61#else
Dirk Eibachfb605942017-02-22 16:07:23 +010062#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30)
63#endif
64
65#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
66#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
67
68#ifdef CONFIG_SPL_BUILD
69#define CONFIG_SYS_MALLOC_SIMPLE
70#endif
71
72#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
73#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
74
Dirk Eibachfb605942017-02-22 16:07:23 +010075#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
76/* SPL related MMC defines */
Dirk Eibachfb605942017-02-22 16:07:23 +010077#ifdef CONFIG_SPL_BUILD
78#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
79#endif
80#endif
81
82/*
83 * Environment Configuration
84 */
Dirk Eibachfb605942017-02-22 16:07:23 +010085
Mario Six790d8442018-03-28 14:38:20 +020086#define CONFIG_HOSTNAME "ccdc"
Dirk Eibachfb605942017-02-22 16:07:23 +010087#define CONFIG_ROOTPATH "/opt/nfsroot"
88#define CONFIG_BOOTFILE "ccdc.img"
89
Dirk Eibachfb605942017-02-22 16:07:23 +010090#define CONFIG_EXTRA_ENV_SETTINGS \
91 "netdev=eth1\0" \
92 "consoledev=ttyS1\0" \
93 "u-boot=u-boot.bin\0" \
94 "bootfile_addr=1000000\0" \
95 "keyprogram_addr=3000000\0" \
96 "keyprogram_file=keyprogram.img\0" \
97 "fdtfile=controlcenterdc.dtb\0" \
98 "load=tftpboot ${loadaddr} ${u-boot}\0" \
99 "mmcdev=0:2\0" \
100 "update=sf probe 1:0;" \
101 " sf erase 0 +${filesize};" \
102 " sf write ${fileaddr} 0 ${filesize}\0" \
103 "upd=run load update\0" \
104 "fdt_high=0x10000000\0" \
105 "initrd_high=0x10000000\0" \
106 "loadkeyprogram=tpm flush_keys;" \
107 " mmc rescan;" \
108 " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
109 " source ${keyprogram_addr}:script@1\0" \
110 "gpio1=gpio@22_25\0" \
111 "gpio2=A29\0" \
112 "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \
113 "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \
114 "bootfail=for i in ${blinkseq}; do" \
115 " if test $i -eq 0; then" \
116 " gpio clear ${gpio1}; gpio set ${gpio2};" \
117 " elif test $i -eq 1; then" \
118 " gpio clear ${gpio1}; gpio clear ${gpio2};" \
119 " elif test $i -eq 2; then" \
120 " gpio set ${gpio1}; gpio set ${gpio2};" \
121 " else;" \
122 " gpio clear ${gpio1}; gpio set ${gpio2};" \
123 " fi; sleep 0.12; done\0"
124
Tom Rini9aed2af2021-08-19 14:29:00 -0400125#define NFSBOOTCOMMAND \
Dirk Eibachfb605942017-02-22 16:07:23 +0100126 "setenv bootargs root=/dev/nfs rw " \
127 "nfsroot=${serverip}:${rootpath} " \
128 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \
129 "console=${consoledev},${baudrate} ${othbootargs}; " \
130 "tftpboot ${bootfile_addr} ${bootfile}; " \
131 "bootm ${bootfile_addr}"
132
Tom Rini9aed2af2021-08-19 14:29:00 -0400133#define MMCBOOTCOMMAND \
Dirk Eibachfb605942017-02-22 16:07:23 +0100134 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
135 "console=${consoledev},${baudrate} ${othbootargs}; " \
136 "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \
137 "bootm ${bootfile_addr}"
138
139#define CONFIG_BOOTCOMMAND \
140 "if env exists keyprogram; then;" \
141 " setenv keyprogram; run nfsboot;" \
142 " fi;" \
143 " run dobootfail"
144
145/*
146 * mv-common.h should be defined after CMD configs since it used them
147 * to enable certain macros
148 */
149#include "mv-common.h"
150
151#endif /* _CONFIG_CONTROLCENTERDC_H */