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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00006 */
7
8/*
9 * FPGA support
10 */
11#include <common.h>
12#include <command.h>
wdenk57b2d802003-06-27 21:31:46 +000013#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053014#include <fs.h>
wdenk525d7b62005-01-22 18:13:04 +000015#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000016
wdenk4a9cbbe2002-08-27 09:48:53 +000017/* Local functions */
Michal Simeka888af72013-04-26 13:10:07 +020018static int fpga_get_op(char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000019
20/* Local defines */
21#define FPGA_NONE -1
22#define FPGA_INFO 0
23#define FPGA_LOAD 1
wdenk310b4fc2005-01-09 18:12:51 +000024#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000025#define FPGA_DUMP 3
Stefan Roese5f1cf2d2006-08-15 14:15:51 +020026#define FPGA_LOADMK 4
Michal Simek64c70982014-05-02 13:43:39 +020027#define FPGA_LOADP 5
28#define FPGA_LOADBP 6
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053029#define FPGA_LOADFS 7
wdenk4a9cbbe2002-08-27 09:48:53 +000030
31/* ------------------------------------------------------------------------- */
32/* command form:
33 * fpga <op> <device number> <data addr> <datasize>
34 * where op is 'load', 'dump', or 'info'
35 * If there is no device number field, the fpga environment variable is used.
36 * If there is no data addr field, the fpgadata environment variable is used.
37 * The info command requires no data address field.
38 */
Michal Simeka888af72013-04-26 13:10:07 +020039int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000040{
wdenk1ebf41e2004-01-02 14:00:00 +000041 int op, dev = FPGA_INVALID_DEVICE;
42 size_t data_size = 0;
43 void *fpga_data = NULL;
Michal Simeka888af72013-04-26 13:10:07 +020044 char *devstr = getenv("fpga");
45 char *datastr = getenv("fpgadata");
wdenk1ebf41e2004-01-02 14:00:00 +000046 int rc = FPGA_FAIL;
Stefano Babic67d7f562010-10-19 09:22:52 +020047 int wrong_parms = 0;
Michal Simeka888af72013-04-26 13:10:07 +020048#if defined(CONFIG_FIT)
Marian Balakowiczd79162d2008-03-12 10:33:01 +010049 const char *fit_uname = NULL;
50 ulong fit_addr;
51#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053052#if defined(CONFIG_CMD_FPGA_LOADFS)
53 fpga_fs_info fpga_fsinfo;
54 fpga_fsinfo.fstype = FS_TYPE_ANY;
55#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000056
wdenk1ebf41e2004-01-02 14:00:00 +000057 if (devstr)
Michal Simeka888af72013-04-26 13:10:07 +020058 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenk1ebf41e2004-01-02 14:00:00 +000059 if (datastr)
Michal Simeka888af72013-04-26 13:10:07 +020060 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +000061
wdenk1ebf41e2004-01-02 14:00:00 +000062 switch (argc) {
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053063#if defined(CONFIG_CMD_FPGA_LOADFS)
64 case 9:
65 fpga_fsinfo.blocksize = (unsigned int)
66 simple_strtoul(argv[5], NULL, 16);
67 fpga_fsinfo.interface = argv[6];
68 fpga_fsinfo.dev_part = argv[7];
69 fpga_fsinfo.filename = argv[8];
70#endif
wdenk1ebf41e2004-01-02 14:00:00 +000071 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simeka888af72013-04-26 13:10:07 +020072 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010073
wdenk1ebf41e2004-01-02 14:00:00 +000074 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczd79162d2008-03-12 10:33:01 +010075#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +020076 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
77 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +010078 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +020079 debug("* fpga: subimage '%s' from FIT image ",
80 fit_uname);
81 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010082 } else
83#endif
84 {
Michal Simeka888af72013-04-26 13:10:07 +020085 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +000086 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simeka888af72013-04-26 13:10:07 +020087 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010088 }
Michal Simeka888af72013-04-26 13:10:07 +020089 debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010090
wdenk1ebf41e2004-01-02 14:00:00 +000091 case 3: /* fpga <op> <dev | data addr> */
Michal Simeka888af72013-04-26 13:10:07 +020092 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +000093 debug("%s: device = %d\n", __func__, dev);
wdenk1ebf41e2004-01-02 14:00:00 +000094 /* FIXME - this is a really weak test */
Michal Simeka888af72013-04-26 13:10:07 +020095 if ((argc == 3) && (dev > fpga_count())) {
96 /* must be buffer ptr */
Stefano Babicb69b9a52011-12-28 06:47:01 +000097 debug("%s: Assuming buffer pointer in arg 3\n",
Michal Simeka888af72013-04-26 13:10:07 +020098 __func__);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010099
100#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200101 if (fit_parse_subimage(argv[2], (ulong)fpga_data,
102 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100103 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +0200104 debug("* fpga: subimage '%s' from FIT image ",
105 fit_uname);
106 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100107 } else
108#endif
109 {
Michal Simeka888af72013-04-26 13:10:07 +0200110 fpga_data = (void *)dev;
111 debug("* fpga: cmdline image addr = 0x%08lx\n",
112 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100113 }
114
Stefano Babicb69b9a52011-12-28 06:47:01 +0000115 debug("%s: fpga_data = 0x%x\n",
Michal Simeka888af72013-04-26 13:10:07 +0200116 __func__, (uint)fpga_data);
wdenk1ebf41e2004-01-02 14:00:00 +0000117 dev = FPGA_INVALID_DEVICE; /* reset device num */
118 }
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100119
wdenk1ebf41e2004-01-02 14:00:00 +0000120 case 2: /* fpga <op> */
Michal Simeka888af72013-04-26 13:10:07 +0200121 op = (int)fpga_get_op(argv[1]);
wdenk1ebf41e2004-01-02 14:00:00 +0000122 break;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100123
wdenk1ebf41e2004-01-02 14:00:00 +0000124 default:
Michal Simeka888af72013-04-26 13:10:07 +0200125 debug("%s: Too many or too few args (%d)\n", __func__, argc);
wdenk1ebf41e2004-01-02 14:00:00 +0000126 op = FPGA_NONE; /* force usage display */
127 break;
128 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000129
Stefano Babic67d7f562010-10-19 09:22:52 +0200130 if (dev == FPGA_INVALID_DEVICE) {
131 puts("FPGA device not specified\n");
132 op = FPGA_NONE;
133 }
134
135 switch (op) {
136 case FPGA_NONE:
137 case FPGA_INFO:
138 break;
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530139#if defined(CONFIG_CMD_FPGA_LOADFS)
140 case FPGA_LOADFS:
141 /* Blocksize can be zero */
142 if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
143 !fpga_fsinfo.filename)
144 wrong_parms = 1;
145#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200146 case FPGA_LOAD:
Michal Simek64c70982014-05-02 13:43:39 +0200147 case FPGA_LOADP:
Stefano Babic67d7f562010-10-19 09:22:52 +0200148 case FPGA_LOADB:
Michal Simek64c70982014-05-02 13:43:39 +0200149 case FPGA_LOADBP:
Stefano Babic67d7f562010-10-19 09:22:52 +0200150 case FPGA_DUMP:
151 if (!fpga_data || !data_size)
152 wrong_parms = 1;
153 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530154#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babic67d7f562010-10-19 09:22:52 +0200155 case FPGA_LOADMK:
156 if (!fpga_data)
157 wrong_parms = 1;
158 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530159#endif
Stefano Babic67d7f562010-10-19 09:22:52 +0200160 }
161
162 if (wrong_parms) {
163 puts("Wrong parameters for FPGA request\n");
164 op = FPGA_NONE;
165 }
166
wdenk1ebf41e2004-01-02 14:00:00 +0000167 switch (op) {
168 case FPGA_NONE:
Simon Glassa06dfc72011-12-10 08:44:01 +0000169 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000170
wdenk1ebf41e2004-01-02 14:00:00 +0000171 case FPGA_INFO:
Michal Simeka888af72013-04-26 13:10:07 +0200172 rc = fpga_info(dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000173 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000174
wdenk1ebf41e2004-01-02 14:00:00 +0000175 case FPGA_LOAD:
Michal Simek14663652014-05-02 14:09:30 +0200176 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenk1ebf41e2004-01-02 14:00:00 +0000177 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000178
Michal Simek64c70982014-05-02 13:43:39 +0200179#if defined(CONFIG_CMD_FPGA_LOADP)
180 case FPGA_LOADP:
181 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
182 break;
183#endif
184
wdenk310b4fc2005-01-09 18:12:51 +0000185 case FPGA_LOADB:
Michal Simek14663652014-05-02 14:09:30 +0200186 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk310b4fc2005-01-09 18:12:51 +0000187 break;
Michal Simek64c70982014-05-02 13:43:39 +0200188
189#if defined(CONFIG_CMD_FPGA_LOADBP)
190 case FPGA_LOADBP:
191 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
192 break;
193#endif
wdenk310b4fc2005-01-09 18:12:51 +0000194
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530195#if defined(CONFIG_CMD_FPGA_LOADFS)
196 case FPGA_LOADFS:
197 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
198 break;
199#endif
200
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530201#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200202 case FPGA_LOADMK:
Michal Simeka888af72013-04-26 13:10:07 +0200203 switch (genimg_get_format(fpga_data)) {
Heiko Schocher515eb122014-05-28 11:33:33 +0200204#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100205 case IMAGE_FORMAT_LEGACY:
206 {
Michal Simeka888af72013-04-26 13:10:07 +0200207 image_header_t *hdr =
208 (image_header_t *)fpga_data;
209 ulong data;
Michal Simekead2d422013-10-04 10:51:01 +0200210 uint8_t comp;
211
212 comp = image_get_comp(hdr);
213 if (comp == IH_COMP_GZIP) {
Michal Simekbe09b942014-07-16 10:30:50 +0200214#if defined(CONFIG_GZIP)
Michal Simekead2d422013-10-04 10:51:01 +0200215 ulong image_buf = image_get_data(hdr);
216 data = image_get_load(hdr);
217 ulong image_size = ~0UL;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200218
Michal Simekead2d422013-10-04 10:51:01 +0200219 if (gunzip((void *)data, ~0UL,
220 (void *)image_buf,
221 &image_size) != 0) {
222 puts("GUNZIP: error\n");
223 return 1;
224 }
225 data_size = image_size;
Michal Simekbe09b942014-07-16 10:30:50 +0200226#else
227 puts("Gunzip image is not supported\n");
228 return 1;
229#endif
Michal Simekead2d422013-10-04 10:51:01 +0200230 } else {
231 data = (ulong)image_get_data(hdr);
232 data_size = image_get_data_size(hdr);
233 }
Michal Simek14663652014-05-02 14:09:30 +0200234 rc = fpga_load(dev, (void *)data, data_size,
235 BIT_FULL);
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200236 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100237 break;
Heiko Schocher515eb122014-05-28 11:33:33 +0200238#endif
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100239#if defined(CONFIG_FIT)
240 case IMAGE_FORMAT_FIT:
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100241 {
242 const void *fit_hdr = (const void *)fpga_data;
243 int noffset;
Wolfgang Denk74f9b382011-07-30 13:33:49 +0000244 const void *fit_data;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100245
246 if (fit_uname == NULL) {
Michal Simeka888af72013-04-26 13:10:07 +0200247 puts("No FIT subimage unit name\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100248 return 1;
249 }
250
Michal Simeka888af72013-04-26 13:10:07 +0200251 if (!fit_check_format(fit_hdr)) {
252 puts("Bad FIT image format\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100253 return 1;
254 }
255
256 /* get fpga component image node offset */
Michal Simeka888af72013-04-26 13:10:07 +0200257 noffset = fit_image_get_node(fit_hdr,
258 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100259 if (noffset < 0) {
Michal Simeka888af72013-04-26 13:10:07 +0200260 printf("Can't find '%s' FIT subimage\n",
261 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100262 return 1;
263 }
264
265 /* verify integrity */
Simon Glass7428ad12013-05-07 06:11:57 +0000266 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100267 puts ("Bad Data Hash\n");
268 return 1;
269 }
270
271 /* get fpga subimage data address and length */
Michal Simeka888af72013-04-26 13:10:07 +0200272 if (fit_image_get_data(fit_hdr, noffset,
273 &fit_data, &data_size)) {
274 puts("Fpga subimage data not found\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100275 return 1;
276 }
277
Michal Simek14663652014-05-02 14:09:30 +0200278 rc = fpga_load(dev, fit_data, data_size,
279 BIT_FULL);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100280 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100281 break;
282#endif
283 default:
Michal Simeka888af72013-04-26 13:10:07 +0200284 puts("** Unknown image type\n");
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100285 rc = FPGA_FAIL;
286 break;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200287 }
288 break;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530289#endif
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200290
wdenk1ebf41e2004-01-02 14:00:00 +0000291 case FPGA_DUMP:
Michal Simeka888af72013-04-26 13:10:07 +0200292 rc = fpga_dump(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000293 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000294
wdenk1ebf41e2004-01-02 14:00:00 +0000295 default:
Michal Simeka888af72013-04-26 13:10:07 +0200296 printf("Unknown operation\n");
Simon Glassa06dfc72011-12-10 08:44:01 +0000297 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000298 }
Michal Simeka888af72013-04-26 13:10:07 +0200299 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000300}
301
wdenk4a9cbbe2002-08-27 09:48:53 +0000302/*
303 * Map op to supported operations. We don't use a table since we
304 * would just have to relocate it from flash anyway.
305 */
Michal Simeka888af72013-04-26 13:10:07 +0200306static int fpga_get_op(char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000307{
308 int op = FPGA_NONE;
309
Michal Simeka888af72013-04-26 13:10:07 +0200310 if (!strcmp("info", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000311 op = FPGA_INFO;
Michal Simeka888af72013-04-26 13:10:07 +0200312 else if (!strcmp("loadb", opstr))
wdenk310b4fc2005-01-09 18:12:51 +0000313 op = FPGA_LOADB;
Michal Simeka888af72013-04-26 13:10:07 +0200314 else if (!strcmp("load", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000315 op = FPGA_LOAD;
Michal Simek64c70982014-05-02 13:43:39 +0200316#if defined(CONFIG_CMD_FPGA_LOADP)
317 else if (!strcmp("loadp", opstr))
318 op = FPGA_LOADP;
319#endif
320#if defined(CONFIG_CMD_FPGA_LOADBP)
321 else if (!strcmp("loadbp", opstr))
322 op = FPGA_LOADBP;
323#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530324#if defined(CONFIG_CMD_FPGA_LOADFS)
325 else if (!strcmp("loadfs", opstr))
326 op = FPGA_LOADFS;
327#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530328#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200329 else if (!strcmp("loadmk", opstr))
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200330 op = FPGA_LOADMK;
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530331#endif
Michal Simeka888af72013-04-26 13:10:07 +0200332 else if (!strcmp("dump", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000333 op = FPGA_DUMP;
wdenk4a9cbbe2002-08-27 09:48:53 +0000334
Michal Simeka888af72013-04-26 13:10:07 +0200335 if (op == FPGA_NONE)
336 printf("Unknown fpga operation \"%s\"\n", opstr);
337
wdenk4a9cbbe2002-08-27 09:48:53 +0000338 return op;
339}
340
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530341#if defined(CONFIG_CMD_FPGA_LOADFS)
342U_BOOT_CMD(fpga, 9, 1, do_fpga,
343#else
Michal Simeka888af72013-04-26 13:10:07 +0200344U_BOOT_CMD(fpga, 6, 1, do_fpga,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530345#endif
Michal Simeka888af72013-04-26 13:10:07 +0200346 "loadable FPGA image support",
347 "[operation type] [device number] [image address] [image size]\n"
348 "fpga operations:\n"
349 " dump\t[dev]\t\t\tLoad device to memory buffer\n"
350 " info\t[dev]\t\t\tlist known device information\n"
351 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek64c70982014-05-02 13:43:39 +0200352#if defined(CONFIG_CMD_FPGA_LOADP)
353 " loadp\t[dev] [address] [size]\t"
354 "Load device from memory buffer with partial bitstream\n"
355#endif
Michal Simeka888af72013-04-26 13:10:07 +0200356 " loadb\t[dev] [address] [size]\t"
357 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek64c70982014-05-02 13:43:39 +0200358#if defined(CONFIG_CMD_FPGA_LOADBP)
359 " loadbp\t[dev] [address] [size]\t"
360 "Load device from bitstream buffer with partial bitstream"
361 "(Xilinx only)\n"
362#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530363#if defined(CONFIG_CMD_FPGA_LOADFS)
364 "Load device from filesystem (FAT by default) (Xilinx only)\n"
365 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
366 " [<dev[:part]>] <filename>\n"
367#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530368#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200369 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100370#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200371 "\n"
372 "\tFor loadmk operating on FIT format uImage address must include\n"
373 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100374#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530375#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100376);