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git01.mediatek.com / filogic / uboot / 70be7a2d2d6afd6e0b1399f5f823e386b37a6e01 / . / include / configs / rcar-gen2-common.h
blob: f1f5d07bf81a63b8c45fd606eeda1664d54dbf79 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]2/*
3 * include/configs/rcar-gen2-common.h
4 *
5 * Copyright (C) 2013,2014 Renesas Electronics Corporation
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]6 */
7
8#ifndef __RCAR_GEN2_COMMON_H
9#define __RCAR_GEN2_COMMON_H
10
11#include <asm/arch/rmobile.h>
12
Marek Vasutcf0f72c2018-02-26 20:19:08 +0100[diff] [blame]13#ifdef CONFIG_SPL
14#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec"
15#endif
16
Marek Vasuta5bbe262018-01-07 19:32:56 +0100[diff] [blame]17#ifndef CONFIG_PINCTRL_PFC
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]18#define CONFIG_SH_GPIO_PFC
Marek Vasuta5bbe262018-01-07 19:32:56 +0100[diff] [blame]19#endif
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]20
21/* console */
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]22#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]23#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
24
25#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
26#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]27
28#define CONFIG_SYS_MONITOR_BASE 0x00000000
29#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]30
31/* ENV setting */
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]32
33/* Common ENV setting */
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]34
Marek Vasutdc891972018-05-31 14:42:12 +0200[diff] [blame]35/* SF MTD */
Frieder Schrempfd7be62c2019-10-23 07:41:20 +0000[diff] [blame]36#ifdef CONFIG_SPL_BUILD
Marek Vasut20106932019-02-19 05:07:13 +0100[diff] [blame]37#undef CONFIG_DM_SPI
38#undef CONFIG_DM_SPI_FLASH
Marek Vasutdc891972018-05-31 14:42:12 +0200[diff] [blame]39#endif
40
Marek Vasut41316702018-08-24 21:52:53 +0200[diff] [blame]41/* Timer */
42#define CONFIG_TMU_TIMER
43#define CONFIG_SYS_TIMER_COUNTS_DOWN
44#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
Tom Rini8c70baa2021-12-14 13:36:40 -0500[diff] [blame]45#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8)
Marek Vasut41316702018-08-24 21:52:53 +0200[diff] [blame]46
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +0900[diff] [blame]47#endif /* __RCAR_GEN2_COMMON_H */