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git01.mediatek.com / filogic / uboot / 70a3030b9b8c0f5ca7b949bd4e1c19179928bfec / . / drivers / net / ldpaa_eth / lx2160a.c
blob: 1fbeb0d14b6f429edaa01d77859c7f7eb7659dce [file] [log] [blame]
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5#include <common.h>
6#include <phy.h>
7#include <fsl-mc/ldpaa_wriop.h>
8#include <asm/io.h>
9#include <asm/arch/fsl_serdes.h>
10#include <asm/arch/soc.h>
11
12u32 dpmac_to_devdisr[] = {
13 [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
14 [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
15 [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
16 [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
17 [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
18 [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
19 [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
20 [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
21 [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
22 [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
23 [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
24 [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
25 [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
26 [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
27 [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
28 [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
29 [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
30 [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
31};
32
33static int is_device_disabled(int dpmac_id)
34{
35 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
36 u32 devdisr2 = in_le32(&gur->devdisr2);
37
38 return dpmac_to_devdisr[dpmac_id] & devdisr2;
39}
40
41void wriop_dpmac_disable(int dpmac_id)
42{
43 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
44
45 setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
46}
47
48void wriop_dpmac_enable(int dpmac_id)
49{
50 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
51
52 clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
53}
54
55phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
56{
57 enum srds_prtcl;
58
59 if (is_device_disabled(dpmac_id + 1))
60 return PHY_INTERFACE_MODE_NONE;
61
62 if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
63 return PHY_INTERFACE_MODE_SGMII;
64
65 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
66 return PHY_INTERFACE_MODE_XGMII;
67
68 if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
69 return PHY_INTERFACE_MODE_25G_AUI;
70
71 if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
72 return PHY_INTERFACE_MODE_XLAUI;
73
74 if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
75 return PHY_INTERFACE_MODE_CAUI2;
76
77 if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
78 return PHY_INTERFACE_MODE_CAUI4;
79
80 return PHY_INTERFACE_MODE_NONE;
81}
82
83#ifdef CONFIG_SYS_FSL_HAS_RGMII
84void fsl_rgmii_init(void)
85{
86 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
87 u32 ec;
88
89#ifdef CONFIG_SYS_FSL_EC1
90 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
91 & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
92 ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
93
Pankaj Bansal89245242019-02-08 08:59:24 +0000[diff] [blame]94 if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV))
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]95 wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
96#endif
97
98#ifdef CONFIG_SYS_FSL_EC2
99 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
100 & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
101 ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
102
Pankaj Bansal89245242019-02-08 08:59:24 +0000[diff] [blame]103 if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV))
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]104 wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
105#endif
106}
107#endif