blob: 93e57cf0cf14456ae6c4af1fbfdb633e41871984 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Shadi Ammouri3b386452016-10-27 13:29:41 +02002/*
3 * Copyright (C) 2015 Marvell International Ltd.
4 *
5 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
6 *
7 * Based on:
8 * - drivers/pci/pcie_imx.c
9 * - drivers/pci/pci_mvebu.c
10 * - drivers/pci/pcie_xilinx.c
Shadi Ammouri3b386452016-10-27 13:29:41 +020011 */
12
13#include <common.h>
14#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060015#include <log.h>
Shadi Ammouri3b386452016-10-27 13:29:41 +020016#include <pci.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060017#include <asm/global_data.h>
Shadi Ammouri3b386452016-10-27 13:29:41 +020018#include <asm/io.h>
Konstantin Porotchkin4eb09cd2017-02-08 17:34:13 +020019#include <asm-generic/gpio.h>
Simon Glassdbd79542020-05-10 11:40:11 -060020#include <linux/delay.h>
Shadi Ammouri3b386452016-10-27 13:29:41 +020021
22DECLARE_GLOBAL_DATA_PTR;
23
24/* PCI Config space registers */
25#define PCIE_CONFIG_BAR0 0x10
26#define PCIE_LINK_STATUS_REG 0x80
27#define PCIE_LINK_STATUS_SPEED_OFF 16
28#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
29#define PCIE_LINK_STATUS_WIDTH_OFF 20
30#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
31
32/* Resizable bar capability registers */
33#define RESIZABLE_BAR_CAP 0x250
34#define RESIZABLE_BAR_CTL0 0x254
35#define RESIZABLE_BAR_CTL1 0x258
36
37/* iATU registers */
38#define PCIE_ATU_VIEWPORT 0x900
39#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
40#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
41#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
42#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
43#define PCIE_ATU_CR1 0x904
44#define PCIE_ATU_TYPE_MEM (0x0 << 0)
45#define PCIE_ATU_TYPE_IO (0x2 << 0)
46#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
47#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
48#define PCIE_ATU_CR2 0x908
49#define PCIE_ATU_ENABLE (0x1 << 31)
50#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
51#define PCIE_ATU_LOWER_BASE 0x90C
52#define PCIE_ATU_UPPER_BASE 0x910
53#define PCIE_ATU_LIMIT 0x914
54#define PCIE_ATU_LOWER_TARGET 0x918
55#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
56#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
57#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
58#define PCIE_ATU_UPPER_TARGET 0x91C
59
60#define PCIE_LINK_CAPABILITY 0x7C
61#define PCIE_LINK_CTL_2 0xA0
62#define TARGET_LINK_SPEED_MASK 0xF
63#define LINK_SPEED_GEN_1 0x1
64#define LINK_SPEED_GEN_2 0x2
65#define LINK_SPEED_GEN_3 0x3
66
67#define PCIE_GEN3_RELATED 0x890
68#define GEN3_EQU_DISABLE (1 << 16)
69#define GEN3_ZRXDC_NON_COMP (1 << 0)
70
71#define PCIE_GEN3_EQU_CTRL 0x8A8
72#define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
73
74#define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
75
76#define PCIE_LINK_UP_TIMEOUT_MS 100
77
78#define PCIE_GLOBAL_CONTROL 0x8000
79#define PCIE_APP_LTSSM_EN (1 << 2)
80#define PCIE_DEVICE_TYPE_OFFSET (4)
81#define PCIE_DEVICE_TYPE_MASK (0xF)
82#define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
83#define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
84#define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
85
86#define PCIE_GLOBAL_STATUS 0x8008
87#define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
88#define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
89
90#define PCIE_ARCACHE_TRC 0x8050
91#define PCIE_AWCACHE_TRC 0x8054
92#define ARCACHE_SHAREABLE_CACHEABLE 0x3511
93#define AWCACHE_SHAREABLE_CACHEABLE 0x5311
94
95#define LINK_SPEED_GEN_1 0x1
96#define LINK_SPEED_GEN_2 0x2
97#define LINK_SPEED_GEN_3 0x3
98
99/**
100 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
101 *
102 * @ctrl_base: The base address of the register space
103 * @cfg_base: The base address of the configuration space
104 * @cfg_size: The size of the configuration space which is needed
105 * as it gets written into the PCIE_ATU_LIMIT register
106 * @first_busno: This driver supports multiple PCIe controllers.
107 * first_busno stores the bus number of the PCIe root-port
108 * number which may vary depending on the PCIe setup
109 * (PEX switches etc).
110 */
111struct pcie_dw_mvebu {
112 void *ctrl_base;
113 void *cfg_base;
114 fdt_size_t cfg_size;
115 int first_busno;
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200116
117 /* IO and MEM PCI regions */
118 struct pci_region io;
119 struct pci_region mem;
Shadi Ammouri3b386452016-10-27 13:29:41 +0200120};
121
122static int pcie_dw_get_link_speed(const void *regs_base)
123{
124 return (readl(regs_base + PCIE_LINK_STATUS_REG) &
125 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
126}
127
128static int pcie_dw_get_link_width(const void *regs_base)
129{
130 return (readl(regs_base + PCIE_LINK_STATUS_REG) &
131 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
132}
133
134/**
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200135 * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
136 *
137 * @pcie: Pointer to the PCI controller state
138 * @index: ATU region index
139 * @type: ATU accsess type
140 * @cpu_addr: the physical address for the translation entry
141 * @pci_addr: the pcie bus address for the translation entry
142 * @size: the size of the translation entry
143 */
144static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
145 int type, u64 cpu_addr, u64 pci_addr,
146 u32 size)
147{
148 writel(PCIE_ATU_REGION_OUTBOUND | index,
149 pcie->ctrl_base + PCIE_ATU_VIEWPORT);
150 writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
151 writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
152 writel(lower_32_bits(cpu_addr + size - 1),
153 pcie->ctrl_base + PCIE_ATU_LIMIT);
154 writel(lower_32_bits(pci_addr),
155 pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
156 writel(upper_32_bits(pci_addr),
157 pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
158 writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
159 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
160}
161
162/**
Shadi Ammouri3b386452016-10-27 13:29:41 +0200163 * set_cfg_address() - Configure the PCIe controller config space access
164 *
165 * @pcie: Pointer to the PCI controller state
166 * @d: PCI device to access
167 * @where: Offset in the configuration space
168 *
169 * Configures the PCIe controller to access the configuration space of
170 * a specific PCIe device and returns the address to use for this
171 * access.
172 *
173 * Return: Address that can be used to access the configation space
174 * of the requested device / offset
175 */
176static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
177 pci_dev_t d, uint where)
178{
179 uintptr_t va_address;
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200180 u32 atu_type;
Shadi Ammouri3b386452016-10-27 13:29:41 +0200181
182 /*
183 * Region #0 is used for Outbound CFG space access.
184 * Direction = Outbound
185 * Region Index = 0
186 */
Shadi Ammouri3b386452016-10-27 13:29:41 +0200187
188 if (PCI_BUS(d) == (pcie->first_busno + 1))
189 /* For local bus, change TLP Type field to 4. */
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200190 atu_type = PCIE_ATU_TYPE_CFG0;
Shadi Ammouri3b386452016-10-27 13:29:41 +0200191 else
192 /* Otherwise, change TLP Type field to 5. */
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200193 atu_type = PCIE_ATU_TYPE_CFG1;
Shadi Ammouri3b386452016-10-27 13:29:41 +0200194
195 if (PCI_BUS(d) == pcie->first_busno) {
196 /* Accessing root port configuration space. */
197 va_address = (uintptr_t)pcie->ctrl_base;
198 } else {
Minghuan Liana1c94382017-10-20 10:45:50 +0800199 d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200200 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
201 atu_type, (u64)pcie->cfg_base,
202 d << 8, pcie->cfg_size);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200203 va_address = (uintptr_t)pcie->cfg_base;
204 }
205
206 va_address += where & ~0x3;
207
208 return va_address;
209}
210
211/**
212 * pcie_dw_addr_valid() - Check for valid bus address
213 *
214 * @d: The PCI device to access
215 * @first_busno: Bus number of the PCIe controller root complex
216 *
217 * Return 1 (true) if the PCI device can be accessed by this controller.
218 *
219 * Return: 1 on valid, 0 on invalid
220 */
221static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
222{
223 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
224 return 0;
225 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
226 return 0;
227
228 return 1;
229}
230
231/**
232 * pcie_dw_mvebu_read_config() - Read from configuration space
233 *
234 * @bus: Pointer to the PCI bus
235 * @bdf: Identifies the PCIe device to access
236 * @offset: The offset into the device's configuration space
237 * @valuep: A pointer at which to store the read value
238 * @size: Indicates the size of access to perform
239 *
240 * Read a value of size @size from offset @offset within the configuration
241 * space of the device identified by the bus, device & function numbers in @bdf
242 * on the PCI bus @bus.
243 *
244 * Return: 0 on success
245 */
Simon Glass2a311e82020-01-27 08:49:37 -0700246static int pcie_dw_mvebu_read_config(const struct udevice *bus, pci_dev_t bdf,
Shadi Ammouri3b386452016-10-27 13:29:41 +0200247 uint offset, ulong *valuep,
248 enum pci_size_t size)
249{
250 struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
251 uintptr_t va_address;
252 ulong value;
253
254 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
255 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
256
257 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
258 debug("- out of range\n");
259 *valuep = pci_get_ff(size);
260 return 0;
261 }
262
263 va_address = set_cfg_address(pcie, bdf, offset);
264
265 value = readl(va_address);
266
267 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
268 *valuep = pci_conv_32_to_size(value, offset, size);
269
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200270 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
271 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
272 pcie->io.bus_start, pcie->io.size);
273
Shadi Ammouri3b386452016-10-27 13:29:41 +0200274 return 0;
275}
276
277/**
278 * pcie_dw_mvebu_write_config() - Write to configuration space
279 *
280 * @bus: Pointer to the PCI bus
281 * @bdf: Identifies the PCIe device to access
282 * @offset: The offset into the device's configuration space
283 * @value: The value to write
284 * @size: Indicates the size of access to perform
285 *
286 * Write the value @value of size @size from offset @offset within the
287 * configuration space of the device identified by the bus, device & function
288 * numbers in @bdf on the PCI bus @bus.
289 *
290 * Return: 0 on success
291 */
292static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
293 uint offset, ulong value,
294 enum pci_size_t size)
295{
296 struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
297 uintptr_t va_address;
298 ulong old;
299
300 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
301 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
302 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
303
304 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
305 debug("- out of range\n");
306 return 0;
307 }
308
309 va_address = set_cfg_address(pcie, bdf, offset);
310
311 old = readl(va_address);
312 value = pci_conv_size_to_32(old, value, offset, size);
313 writel(value, va_address);
314
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200315 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
316 PCIE_ATU_TYPE_IO, pcie->io.phys_start,
317 pcie->io.bus_start, pcie->io.size);
318
Shadi Ammouri3b386452016-10-27 13:29:41 +0200319 return 0;
320}
321
322/**
323 * pcie_dw_configure() - Configure link capabilities and speed
324 *
325 * @regs_base: A pointer to the PCIe controller registers
326 * @cap_speed: The capabilities and speed to configure
327 *
328 * Configure the link capabilities and speed in the PCIe root complex.
329 */
330static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
331{
332 /*
333 * TODO (shadi@marvell.com, sr@denx.de):
334 * Need to read the serdes speed from the dts and according to it
335 * configure the PCIe gen
336 */
337
338 /* Set link to GEN 3 */
339 clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
340 TARGET_LINK_SPEED_MASK, cap_speed);
341 clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
342 TARGET_LINK_SPEED_MASK, cap_speed);
343 setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
344}
345
346/**
347 * is_link_up() - Return the link state
348 *
349 * @regs_base: A pointer to the PCIe controller registers
350 *
351 * Return: 1 (true) for active line and 0 (false) for no link
352 */
353static int is_link_up(const void *regs_base)
354{
355 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
356 u32 reg;
357
358 reg = readl(regs_base + PCIE_GLOBAL_STATUS);
359 if ((reg & mask) == mask)
360 return 1;
361
362 return 0;
363}
364
365/**
366 * wait_link_up() - Wait for the link to come up
367 *
368 * @regs_base: A pointer to the PCIe controller registers
369 *
370 * Return: 1 (true) for active line and 0 (false) for no link (timeout)
371 */
372static int wait_link_up(const void *regs_base)
373{
374 unsigned long timeout;
375
376 timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
377 while (!is_link_up(regs_base)) {
378 if (get_timer(0) > timeout)
379 return 0;
380 };
381
382 return 1;
383}
384
385/**
386 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
387 *
388 * @regs_base: A pointer to the PCIe controller registers
389 * @cap_speed: The capabilities and speed to configure
390 *
391 * Configure the PCIe controller root complex depending on the
392 * requested link capabilities and speed.
393 *
394 * Return: 1 (true) for active line and 0 (false) for no link
395 */
396static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
397{
398 if (!is_link_up(regs_base)) {
399 /* Disable LTSSM state machine to enable configuration */
400 clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
401 PCIE_APP_LTSSM_EN);
402 }
403
404 clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
405 PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
406 PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
407
408 /* Set the PCIe master AXI attributes */
409 writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
410 writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
411
412 /* DW pre link configurations */
413 pcie_dw_configure(regs_base, cap_speed);
414
415 if (!is_link_up(regs_base)) {
416 /* Configuration done. Start LTSSM */
417 setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
418 PCIE_APP_LTSSM_EN);
419 }
420
421 /* Check that link was established */
422 if (!wait_link_up(regs_base))
423 return 0;
424
425 /*
426 * Link can be established in Gen 1. still need to wait
427 * till MAC nagaotiation is completed
428 */
429 udelay(100);
430
431 return 1;
432}
433
434/**
Shadi Ammouri3b386452016-10-27 13:29:41 +0200435 * pcie_dw_set_host_bars() - Configure the host BARs
436 *
437 * @regs_base: A pointer to the PCIe controller registers
438 *
439 * Configure the host BARs of the PCIe controller root port so that
440 * PCI(e) devices may access the system memory.
441 */
442static void pcie_dw_set_host_bars(const void *regs_base)
443{
444 u32 size = gd->ram_size;
445 u64 max_size;
446 u32 reg;
447 u32 bar0;
448
449 /* Verify the maximal BAR size */
450 reg = readl(regs_base + RESIZABLE_BAR_CAP);
451 max_size = 1ULL << (5 + (reg + (1 << 4)));
452
453 if (size > max_size) {
454 size = max_size;
455 printf("Warning: PCIe BARs can't map all DRAM space\n");
456 }
457
458 /* Set the BAR base and size towards DDR */
459 bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
460 bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
461 writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
462
463 reg = ((size >> 20) - 1) << 12;
464 writel(size, regs_base + RESIZABLE_BAR_CTL0);
465}
466
467/**
468 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
469 *
470 * @dev: A pointer to the device being operated on
471 *
472 * Probe for an active link on the PCIe bus and configure the controller
473 * to enable this port.
474 *
475 * Return: 0 on success, else -ENODEV
476 */
477static int pcie_dw_mvebu_probe(struct udevice *dev)
478{
479 struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
480 struct udevice *ctlr = pci_get_controller(dev);
481 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
Simon Glassfa4689a2019-12-06 21:41:35 -0700482#if CONFIG_IS_ENABLED(DM_GPIO)
Konstantin Porotchkin4eb09cd2017-02-08 17:34:13 +0200483 struct gpio_desc reset_gpio;
484
485 gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
486 GPIOD_IS_OUT);
487 /*
488 * Issue reset to add-in card trough the dedicated GPIO.
489 * Some boards are connecting the card reset pin to common system
490 * reset wire and others are using separate GPIO port.
491 * In the last case we have to release a reset of the addon card
492 * using this GPIO.
493 */
494 if (dm_gpio_is_valid(&reset_gpio)) {
Baruch Siach6e599c62019-02-03 15:15:39 +0200495 dm_gpio_set_value(&reset_gpio, 1); /* assert */
496 mdelay(200);
497 dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
Konstantin Porotchkin4eb09cd2017-02-08 17:34:13 +0200498 mdelay(200);
499 }
500#else
501 debug("PCIE Reset on GPIO support is missing\n");
Simon Glassfa4689a2019-12-06 21:41:35 -0700502#endif /* DM_GPIO */
Shadi Ammouri3b386452016-10-27 13:29:41 +0200503
Simon Glass75e534b2020-12-16 21:20:07 -0700504 pcie->first_busno = dev_seq(dev);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200505
506 /* Don't register host if link is down */
507 if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
Simon Glass75e534b2020-12-16 21:20:07 -0700508 printf("PCIE-%d: Link down\n", dev_seq(dev));
Konstantin Porotchkind4739d32017-03-28 18:36:34 +0300509 } else {
Simon Glass75e534b2020-12-16 21:20:07 -0700510 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
Konstantin Porotchkind4739d32017-03-28 18:36:34 +0300511 pcie_dw_get_link_speed(pcie->ctrl_base),
512 pcie_dw_get_link_width(pcie->ctrl_base),
513 hose->first_busno);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200514 }
515
Igal Libermanf09ac1a2018-02-14 19:25:23 +0200516 /* Store the IO and MEM windows settings for future use by the ATU */
517 pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
518 pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
519 pcie->io.size = hose->regions[0].size; /* IO size */
520
521 pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
522 pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
523 pcie->mem.size = hose->regions[1].size; /* MEM size */
524
525 pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
526 PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
527 pcie->mem.bus_start, pcie->mem.size);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200528
529 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
530 clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
531 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
532
533 pcie_dw_set_host_bars(pcie->ctrl_base);
534
535 return 0;
536}
537
538/**
Simon Glassaad29ae2020-12-03 16:55:21 -0700539 * pcie_dw_mvebu_of_to_plat() - Translate from DT to device state
Shadi Ammouri3b386452016-10-27 13:29:41 +0200540 *
541 * @dev: A pointer to the device being operated on
542 *
543 * Translate relevant data from the device tree pertaining to device @dev into
544 * state that the driver will later make use of. This state is stored in the
545 * device's private data structure.
546 *
547 * Return: 0 on success, else -EINVAL
548 */
Simon Glassaad29ae2020-12-03 16:55:21 -0700549static int pcie_dw_mvebu_of_to_plat(struct udevice *dev)
Shadi Ammouri3b386452016-10-27 13:29:41 +0200550{
551 struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
552
553 /* Get the controller base address */
Simon Glassba1dea42017-05-17 17:18:05 -0600554 pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
Shadi Ammouri3b386452016-10-27 13:29:41 +0200555 if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
556 return -EINVAL;
557
558 /* Get the config space base address and size */
Simon Glassba1dea42017-05-17 17:18:05 -0600559 pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
Shadi Ammouri3b386452016-10-27 13:29:41 +0200560 &pcie->cfg_size);
561 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
562 return -EINVAL;
563
564 return 0;
565}
566
567static const struct dm_pci_ops pcie_dw_mvebu_ops = {
568 .read_config = pcie_dw_mvebu_read_config,
569 .write_config = pcie_dw_mvebu_write_config,
570};
571
572static const struct udevice_id pcie_dw_mvebu_ids[] = {
573 { .compatible = "marvell,armada8k-pcie" },
574 { }
575};
576
577U_BOOT_DRIVER(pcie_dw_mvebu) = {
578 .name = "pcie_dw_mvebu",
579 .id = UCLASS_PCI,
580 .of_match = pcie_dw_mvebu_ids,
581 .ops = &pcie_dw_mvebu_ops,
Simon Glassaad29ae2020-12-03 16:55:21 -0700582 .of_to_plat = pcie_dw_mvebu_of_to_plat,
Shadi Ammouri3b386452016-10-27 13:29:41 +0200583 .probe = pcie_dw_mvebu_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700584 .priv_auto = sizeof(struct pcie_dw_mvebu),
Shadi Ammouri3b386452016-10-27 13:29:41 +0200585};