Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Sysam stmark2 board configuration |
| 4 | * |
| 5 | * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __STMARK2_CONFIG_H |
| 9 | #define __STMARK2_CONFIG_H |
| 10 | |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 11 | #define CONFIG_HOSTNAME "stmark2" |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 12 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 13 | #define CONFIG_SYS_UART_PORT 0 |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 14 | |
| 15 | #define LDS_BOARD_TEXT \ |
| 16 | board/sysam/stmark2/sbf_dram_init.o (.text*) |
| 17 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 18 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 19 | "kern_size=0x700000\0" \ |
| 20 | "loadaddr=0x40001000\0" \ |
| 21 | "-(rootfs)\0" \ |
| 22 | "update_uboot=loady ${loadaddr}; " \ |
| 23 | "sf probe 0:1 50000000; " \ |
| 24 | "sf erase 0 0x80000; " \ |
| 25 | "sf write ${loadaddr} 0 ${filesize}\0" \ |
| 26 | "update_kernel=loady ${loadaddr}; " \ |
| 27 | "setenv kern_size ${filesize}; saveenv; " \ |
| 28 | "sf probe 0:1 50000000; " \ |
| 29 | "sf erase 0x100000 0x700000; " \ |
| 30 | "sf write ${loadaddr} 0x100000 ${filesize}\0" \ |
| 31 | "update_rootfs=loady ${loadaddr}; " \ |
| 32 | "sf probe 0:1 50000000; " \ |
| 33 | "sf erase 0x00800000 0x100000; " \ |
| 34 | "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ |
| 35 | "" |
| 36 | |
| 37 | /* Realtime clock */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 38 | #define CONFIG_RTC_MCFRRTC |
| 39 | #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 |
| 40 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 41 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 |
| 42 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 43 | /* Input, PCI, Flexbus, and VCO */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 44 | |
| 45 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 46 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 47 | #define CONFIG_SYS_MBAR 0xFC000000 |
| 48 | |
| 49 | /* |
| 50 | * Definitions for initial stack pointer and data area (in internal SRAM) |
| 51 | */ |
| 52 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
| 53 | /* End of used area in internal SRAM */ |
| 54 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
| 55 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
Tom Rini | d5342e8 | 2022-05-24 13:40:05 -0400 | [diff] [blame] | 56 | #define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 57 | GENERATED_GBL_DATA_SIZE) - 32) |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 58 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
| 59 | |
| 60 | /* |
| 61 | * Start addresses for the final memory configuration |
| 62 | * (Set up by the startup code) |
| 63 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 64 | */ |
| 65 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| 66 | #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ |
| 67 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_DRAM_TEST |
| 69 | |
| 70 | #if defined(CONFIG_CF_SBF) |
| 71 | #define CONFIG_SERIAL_BOOT |
| 72 | #endif |
| 73 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 74 | /* Reserve 256 kB for Monitor */ |
| 75 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * For booting Linux, the board info and command line data |
| 79 | * have to be in the first 8 MB of memory, since this is |
| 80 | * the maximum mapped by the Linux kernel during initialization ?? |
| 81 | */ |
| 82 | /* Initial Memory map for Linux */ |
| 83 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ |
| 84 | (CONFIG_SYS_SDRAM_SIZE << 20)) |
| 85 | |
| 86 | /* Configuration for environment |
| 87 | * Environment is embedded in u-boot in the second sector of the flash |
| 88 | */ |
| 89 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 90 | /* Cache Configuration */ |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 91 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 92 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
| 93 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 94 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
| 95 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
| 96 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) |
| 97 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ |
| 98 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 99 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 100 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ |
| 101 | CF_CACR_ICINVA | CF_CACR_EUSP) |
| 102 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ |
| 103 | CF_CACR_DEC | CF_CACR_DDCM_P | \ |
| 104 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) |
| 105 | |
| 106 | #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 107 | CONFIG_SYS_INIT_RAM_SIZE - 12) |
| 108 | |
Angelo Dureghello | 67c4e48 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 109 | #endif /* __STMARK2_CONFIG_H */ |