blob: 8dd6b4d40e778015fe94f11ac2f62417c9b0f93f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peng Fanb5a90292017-02-22 16:21:43 +08002/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
Peng Fanb5a90292017-02-22 16:21:43 +08004 */
Simon Glass1e268642020-05-10 11:39:55 -06005
6#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07007#include <cpu_func.h>
Simon Glassa7b51302019-11-14 12:57:46 -07008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Peng Fanb5a90292017-02-22 16:21:43 +080010#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/sys_proto.h>
Peng Fanb1d6be92019-07-22 01:24:37 +000014#include <asm/mach-imx/boot_mode.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020015#include <asm/mach-imx/hab.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Peng Fanb5a90292017-02-22 16:21:43 +080017
Fabio Estevamd1d70232019-11-05 09:47:51 -030018#define PMC0_BASE_ADDR 0x410a1000
19#define PMC0_CTRL 0x28
20#define PMC0_CTRL_LDOEN BIT(31)
21#define PMC0_CTRL_LDOOKDIS BIT(30)
22#define PMC0_CTRL_PMC1ON BIT(24)
23#define PMC1_BASE_ADDR 0x40400000
24#define PMC1_RUN 0x8
25#define PMC1_STOP 0x10
26#define PMC1_VLPS 0x14
Fabio Estevam04c71e72019-11-05 09:47:52 -030027#define PMC1_LDOVL_SHIFT 16
28#define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
29#define PMC1_LDOVL_900 0x1e
30#define PMC1_LDOVL_950 0x23
Fabio Estevamd1d70232019-11-05 09:47:51 -030031#define PMC1_STATUS 0x20
32#define PMC1_STATUS_LDOVLF BIT(8)
33
Peng Fanb5a90292017-02-22 16:21:43 +080034static char *get_reset_cause(char *);
35
Stefano Babicf8b509b2019-09-20 08:47:53 +020036#if defined(CONFIG_IMX_HAB)
Peng Fana26ba6d2017-02-22 16:21:53 +080037struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
38 .bank = 29,
39 .word = 6,
40};
41#endif
42
Peng Fan67753cf2019-07-22 01:25:05 +000043#define ROM_VERSION_ADDR 0x80
Peng Fanb5a90292017-02-22 16:21:43 +080044u32 get_cpu_rev(void)
45{
Peng Fan67753cf2019-07-22 01:25:05 +000046 /* Check the ROM version for cpu revision */
47 u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
48
49 return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
Peng Fanb5a90292017-02-22 16:21:43 +080050}
51
52#ifdef CONFIG_REVISION_TAG
53u32 __weak get_board_rev(void)
54{
55 return get_cpu_rev();
56}
57#endif
58
59enum bt_mode get_boot_mode(void)
60{
61 u32 bt0_cfg = 0;
62
63 bt0_cfg = readl(CMC0_RBASE + 0x40);
64 bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
65
66 if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
67 /* No low power boot */
68 if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
69 return DUAL_BOOT;
70 else
71 return SINGLE_BOOT;
72 }
73
74 return LOW_POWER_BOOT;
75}
76
77int arch_cpu_init(void)
78{
79 return 0;
80}
81
82#ifdef CONFIG_BOARD_POSTCLK_INIT
83int board_postclk_init(void)
84{
85 return 0;
86}
87#endif
88
89#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
90#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
91#define REFRESH_WORD0 0xA602 /* 1st refresh word */
92#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
93
94static void disable_wdog(u32 wdog_base)
95{
96 writel(UNLOCK_WORD0, (wdog_base + 0x04));
97 writel(UNLOCK_WORD1, (wdog_base + 0x04));
98 writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
99 writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
100 writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
101
102 writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
103 writel(REFRESH_WORD1, (wdog_base + 0x04));
104}
105
106void init_wdog(void)
107{
108 /*
109 * ROM will configure WDOG1, disable it or enable it
110 * depending on FUSE. The update bit is set for reconfigurable.
111 * We have to use unlock sequence to reconfigure it.
112 * WDOG2 is not touched by ROM, so it will have default value
113 * which is enabled. We can directly configure it.
114 * To simplify the codes, we still use same reconfigure
115 * process as WDOG1. Because the update bit is not set for
116 * WDOG2, the unlock sequence won't take effect really.
117 * It actually directly configure the wdog.
118 * In this function, we will disable both WDOG1 and WDOG2,
119 * and set update bit for both. So that kernel can reconfigure them.
120 */
121 disable_wdog(WDG1_RBASE);
122 disable_wdog(WDG2_RBASE);
123}
124
Fabio Estevam93ee0ab2020-02-03 09:01:09 -0300125static bool ldo_mode_is_enabled(void)
126{
127 unsigned int reg;
128
129 reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
130 if (reg & PMC0_CTRL_LDOEN)
131 return true;
132 else
133 return false;
134}
135
Jorge Ramirez-Ortiz409cf642020-01-17 10:50:25 +0100136#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
Fabio Estevamd1d70232019-11-05 09:47:51 -0300137#if defined(CONFIG_LDO_ENABLED_MODE)
138static void init_ldo_mode(void)
139{
140 unsigned int reg;
141
Fabio Estevam93ee0ab2020-02-03 09:01:09 -0300142 if (ldo_mode_is_enabled())
143 return;
144
Fabio Estevamd1d70232019-11-05 09:47:51 -0300145 /* Set LDOOKDIS */
146 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
147
148 /* Set LDOVL to 0.95V in PMC1_RUN */
149 reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
Fabio Estevam04c71e72019-11-05 09:47:52 -0300150 reg &= ~PMC1_LDOVL_MASK;
151 reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
Fabio Estevamd1d70232019-11-05 09:47:51 -0300152 writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
153
154 /* Wait for LDOVLF to be cleared */
155 reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
156 while (reg & PMC1_STATUS_LDOVLF)
157 ;
158
159 /* Set LDOVL to 0.95V in PMC1_STOP */
160 reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
Fabio Estevam04c71e72019-11-05 09:47:52 -0300161 reg &= ~PMC1_LDOVL_MASK;
162 reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
Fabio Estevamd1d70232019-11-05 09:47:51 -0300163 writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
164
165 /* Set LDOVL to 0.90V in PMC1_VLPS */
166 reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
Fabio Estevam04c71e72019-11-05 09:47:52 -0300167 reg &= ~PMC1_LDOVL_MASK;
168 reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
Fabio Estevamd1d70232019-11-05 09:47:51 -0300169 writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
170
171 /* Set LDOEN bit */
172 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
173
174 /* Set the PMC1ON bit */
175 setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
176}
177#endif
Peng Fanb5a90292017-02-22 16:21:43 +0800178
179void s_init(void)
180{
181 /* Disable wdog */
182 init_wdog();
183
184 /* clock configuration. */
185 clock_init();
186
Bai Pingb1b61c62019-07-22 01:24:42 +0000187 if (soc_rev() < CHIP_REV_2_0) {
188 /* enable dumb pmic */
189 writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
190 }
Fabio Estevamd1d70232019-11-05 09:47:51 -0300191
192#if defined(CONFIG_LDO_ENABLED_MODE)
193 init_ldo_mode();
194#endif
Peng Fanb5a90292017-02-22 16:21:43 +0800195 return;
196}
Jorge Ramirez-Ortiz409cf642020-01-17 10:50:25 +0100197#endif
Peng Fanb5a90292017-02-22 16:21:43 +0800198
199#ifndef CONFIG_ULP_WATCHDOG
200void reset_cpu(ulong addr)
201{
202 setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
203 while (1)
204 ;
205}
206#endif
207
208#if defined(CONFIG_DISPLAY_CPUINFO)
209const char *get_imx_type(u32 imxtype)
210{
211 return "7ULP";
212}
213
214int print_cpuinfo(void)
215{
216 u32 cpurev;
217 char cause[18];
218
219 cpurev = get_cpu_rev();
220
221 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
222 get_imx_type((cpurev & 0xFF000) >> 12),
223 (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
224 mxc_get_clock(MXC_ARM_CLK) / 1000000);
225
226 printf("Reset cause: %s\n", get_reset_cause(cause));
227
228 printf("Boot mode: ");
229 switch (get_boot_mode()) {
230 case LOW_POWER_BOOT:
231 printf("Low power boot\n");
232 break;
233 case DUAL_BOOT:
234 printf("Dual boot\n");
235 break;
236 case SINGLE_BOOT:
237 default:
238 printf("Single boot\n");
239 break;
240 }
241
Fabio Estevama320c122019-11-05 09:47:50 -0300242 if (ldo_mode_is_enabled())
243 printf("PMC1: LDO enabled mode\n");
244 else
245 printf("PMC1: LDO bypass mode\n");
246
Peng Fanb5a90292017-02-22 16:21:43 +0800247 return 0;
248}
249#endif
250
251#define CMC_SRS_TAMPER (1 << 31)
252#define CMC_SRS_SECURITY (1 << 30)
253#define CMC_SRS_TZWDG (1 << 29)
254#define CMC_SRS_JTAG_RST (1 << 28)
255#define CMC_SRS_CORE1 (1 << 16)
256#define CMC_SRS_LOCKUP (1 << 15)
257#define CMC_SRS_SW (1 << 14)
258#define CMC_SRS_WDG (1 << 13)
259#define CMC_SRS_PIN_RESET (1 << 8)
260#define CMC_SRS_WARM (1 << 4)
261#define CMC_SRS_HVD (1 << 3)
262#define CMC_SRS_LVD (1 << 2)
263#define CMC_SRS_POR (1 << 1)
264#define CMC_SRS_WUP (1 << 0)
265
266static u32 reset_cause = -1;
267
268static char *get_reset_cause(char *ret)
269{
270 u32 cause1, cause = 0, srs = 0;
271 u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
272 u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
273
274 if (!ret)
275 return "null";
276
277 srs = readl(reg_srs);
278 cause1 = readl(reg_ssrs);
279 writel(cause1, reg_ssrs);
280
281 reset_cause = cause1;
282
283 cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
284
285 switch (cause) {
286 case CMC_SRS_POR:
287 sprintf(ret, "%s", "POR");
288 break;
289 case CMC_SRS_WUP:
290 sprintf(ret, "%s", "WUP");
291 break;
292 case CMC_SRS_WARM:
293 cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
294 CMC_SRS_JTAG_RST);
295 switch (cause) {
296 case CMC_SRS_WDG:
297 sprintf(ret, "%s", "WARM-WDG");
298 break;
299 case CMC_SRS_SW:
300 sprintf(ret, "%s", "WARM-SW");
301 break;
302 case CMC_SRS_JTAG_RST:
303 sprintf(ret, "%s", "WARM-JTAG");
304 break;
305 default:
306 sprintf(ret, "%s", "WARM-UNKN");
307 break;
308 }
309 break;
310 default:
311 sprintf(ret, "%s-%X", "UNKN", cause1);
312 break;
313 }
314
315 debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
316 return ret;
317}
318
319#ifdef CONFIG_ENV_IS_IN_MMC
320__weak int board_mmc_get_env_dev(int devno)
321{
322 return CONFIG_SYS_MMC_ENV_DEV;
323}
324
325int mmc_get_env_dev(void)
326{
327 int devno = 0;
328 u32 bt1_cfg = 0;
329
330 /* If not boot from sd/mmc, use default value */
331 if (get_boot_mode() == LOW_POWER_BOOT)
332 return CONFIG_SYS_MMC_ENV_DEV;
333
334 bt1_cfg = readl(CMC1_RBASE + 0x40);
335 devno = (bt1_cfg >> 9) & 0x7;
336
337 return board_mmc_get_env_dev(devno);
338}
339#endif
Peng Fanb1d6be92019-07-22 01:24:37 +0000340
341enum boot_device get_boot_device(void)
342{
343 struct bootrom_sw_info **p =
344 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
345
346 enum boot_device boot_dev = SD1_BOOT;
347 u8 boot_type = (*p)->boot_dev_type;
348 u8 boot_instance = (*p)->boot_dev_instance;
349
350 switch (boot_type) {
351 case BOOT_TYPE_SD:
352 boot_dev = boot_instance + SD1_BOOT;
353 break;
354 case BOOT_TYPE_MMC:
355 boot_dev = boot_instance + MMC1_BOOT;
356 break;
357 case BOOT_TYPE_USB:
358 boot_dev = USB_BOOT;
359 break;
360 default:
361 break;
362 }
363
364 return boot_dev;
365}