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Hans de Goedeb728aae2015-01-21 16:14:00 +01001/* DRAM parameters for auto dram configuration on sun5i and sun7i */
Hans de Goede7ee8cd12015-01-17 22:31:30 +01002
Simon Glass97589732020-05-10 11:40:02 -06003#include <init.h>
Hans de Goede7ee8cd12015-01-17 22:31:30 +01004#include <asm/arch/dram.h>
5
6static struct dram_para dram_para = {
7 .clock = CONFIG_DRAM_CLK,
Siarhei Siamashka47359bb2015-02-01 00:27:06 +02008 .mbus_clock = CONFIG_DRAM_MBUS_CLK,
Giulio Benetti0fe7a5f2021-12-03 00:57:54 +01009 .type = DRAM_MEMORY_TYPE_DDR3,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010010 .rank_num = 1,
11 .density = 0,
12 .io_width = 0,
13 .bus_width = 0,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010014 .zq = CONFIG_DRAM_ZQ,
Hans de Goedeffdc05c2015-05-13 15:00:46 +020015 .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
Hans de Goede7ee8cd12015-01-17 22:31:30 +010016 .size = 0,
Siarhei Siamashka9900db12015-02-01 00:27:05 +020017#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
18 .cas = 9,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010019 .tpr0 = 0x42d899b7,
20 .tpr1 = 0xa090,
21 .tpr2 = 0x22a00,
Siarhei Siamashka9900db12015-02-01 00:27:05 +020022 .emr2 = 0x10,
23#else
24# include "dram_timings_sun4i.h"
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020025 .active_windowing = 1,
Siarhei Siamashka9900db12015-02-01 00:27:05 +020026#endif
Adam Sampsone954e922015-02-23 20:44:10 +000027 .tpr3 = CONFIG_DRAM_TPR3,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010028 .tpr4 = 0,
29 .tpr5 = 0,
30 .emr1 = CONFIG_DRAM_EMR1,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010031 .emr3 = 0,
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020032 .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
Hans de Goede7ee8cd12015-01-17 22:31:30 +010033};
34
35unsigned long sunxi_dram_init(void)
36{
37 return dramc_init(&dram_para);
38}