Tom Warren | 85f0ee4 | 2011-05-31 10:30:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2009 SAMSUNG Electronics |
| 3 | * Minkyu Kang <mk7.kang@samsung.com> |
| 4 | * Portions Copyright (C) 2011 NVIDIA Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | * |
| 20 | */ |
| 21 | |
| 22 | #ifndef __TEGRA2_MMC_H_ |
| 23 | #define __TEGRA2_MMC_H_ |
| 24 | |
| 25 | #define TEGRA2_SDMMC1_BASE 0xC8000000 |
| 26 | #define TEGRA2_SDMMC2_BASE 0xC8000200 |
| 27 | #define TEGRA2_SDMMC3_BASE 0xC8000400 |
| 28 | #define TEGRA2_SDMMC4_BASE 0xC8000600 |
| 29 | |
| 30 | #ifndef __ASSEMBLY__ |
| 31 | struct tegra2_mmc { |
| 32 | unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ |
| 33 | unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ |
| 34 | unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ |
| 35 | unsigned int argument; /* _ARGUMENT_0 */ |
| 36 | unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ |
| 37 | unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ |
| 38 | unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ |
| 39 | unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ |
| 40 | unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ |
| 41 | unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ |
| 42 | unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ |
| 43 | unsigned int prnsts; /* _PRESENT_STATE_0 */ |
| 44 | unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ |
| 45 | unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ |
| 46 | unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ |
| 47 | unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ |
| 48 | unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ |
| 49 | unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ |
| 50 | unsigned char swrst; /* _SW_RESET_ 31:24 */ |
| 51 | unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ |
| 52 | unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ |
| 53 | unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ |
| 54 | unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ |
| 55 | unsigned char res1[2]; /* _RESERVED 31:16 */ |
| 56 | unsigned int capareg; /* _CAPABILITIES_0 */ |
| 57 | unsigned char res2[4]; /* RESERVED, offset 44h-47h */ |
| 58 | unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ |
| 59 | unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ |
| 60 | unsigned short setacmd12err; /* offset 50h */ |
| 61 | unsigned short setinterr; /* offset 52h */ |
| 62 | unsigned char admaerr; /* offset 54h */ |
| 63 | unsigned char res4[3]; /* RESERVED, offset 55h-57h */ |
| 64 | unsigned long admaaddr; /* offset 58h-5Fh */ |
| 65 | unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ |
| 66 | unsigned short slotintstatus; /* offset FCh */ |
| 67 | unsigned short hcver; /* HOST Version */ |
| 68 | unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ |
| 69 | }; |
| 70 | |
Anton staaf | 0dfb31c | 2011-11-10 11:56:49 +0000 | [diff] [blame] | 71 | #define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) |
| 72 | #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) |
| 73 | #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) |
| 74 | #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) |
| 75 | |
| 76 | #define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) |
| 77 | #define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) |
| 78 | #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) |
| 79 | #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) |
| 80 | #define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) |
| 81 | |
| 82 | #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) |
| 83 | #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) |
| 84 | #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) |
| 85 | #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) |
| 86 | #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) |
| 87 | |
| 88 | #define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) |
| 89 | #define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) |
| 90 | #define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) |
| 91 | |
| 92 | #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) |
| 93 | #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) |
| 94 | |
| 95 | #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) |
| 96 | #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) |
| 97 | #define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) |
| 98 | |
| 99 | #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 |
| 100 | #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) |
| 101 | |
| 102 | #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) |
| 103 | #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) |
| 104 | #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) |
| 105 | |
| 106 | #define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) |
| 107 | #define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) |
| 108 | #define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) |
| 109 | #define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) |
| 110 | #define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) |
| 111 | |
| 112 | #define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) |
| 113 | #define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) |
| 114 | #define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) |
| 115 | #define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) |
| 116 | #define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) |
| 117 | |
| 118 | #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) |
| 119 | |
Tom Warren | 85f0ee4 | 2011-05-31 10:30:37 +0000 | [diff] [blame] | 120 | struct mmc_host { |
| 121 | struct tegra2_mmc *reg; |
| 122 | unsigned int version; /* SDHCI spec. version */ |
| 123 | unsigned int clock; /* Current clock (MHz) */ |
| 124 | unsigned int base; /* Base address, SDMMC1/2/3/4 */ |
Simon Glass | c2ea5e4 | 2011-09-21 12:40:04 +0000 | [diff] [blame] | 125 | enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ |
Stephen Warren | fba8754 | 2011-10-31 06:51:36 +0000 | [diff] [blame] | 126 | int pwr_gpio; /* Power GPIO */ |
| 127 | int cd_gpio; /* Change Detect GPIO */ |
Tom Warren | 85f0ee4 | 2011-05-31 10:30:37 +0000 | [diff] [blame] | 128 | }; |
| 129 | |
Stephen Warren | fba8754 | 2011-10-31 06:51:36 +0000 | [diff] [blame] | 130 | int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); |
Tom Warren | 85f0ee4 | 2011-05-31 10:30:37 +0000 | [diff] [blame] | 131 | |
| 132 | #endif /* __ASSEMBLY__ */ |
| 133 | #endif /* __TEGRA2_MMC_H_ */ |