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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
5 select CPU_V7
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02008 help
9 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
10 including NEON and GPU, Mali-400 graphics, several DDR3 options
11 and video codec support. Peripherals include Gigabit Ethernet,
12 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
13
Heiko Stübneref6db5e2017-02-18 19:46:36 +010014config ROCKCHIP_RK3188
15 bool "Support Rockchip RK3188"
16 select CPU_V7
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080017 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010018 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010019 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020020 select SPL_CLK
21 select SPL_PINCTRL
22 select SPL_REGMAP
23 select SPL_SYSCON
24 select SPL_RAM
25 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020026 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020027 select BOARD_LATE_INIT
Heiko Stübneref6db5e2017-02-18 19:46:36 +010028 select ROCKCHIP_BROM_HELPER
29 help
30 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
31 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
32 video interfaces, several memory options and video codec support.
33 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
34 UART, SPI, I2C and PWMs.
35
Kever Yang57d4dbf2017-06-23 17:17:52 +080036config ROCKCHIP_RK322X
37 bool "Support Rockchip RK3228/RK3229"
38 select CPU_V7
39 select SUPPORT_SPL
40 select SPL
41 select ROCKCHIP_BROM_HELPER
42 select DEBUG_UART_BOARD_INIT
43 help
44 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
45 including NEON and GPU, Mali-400 graphics, several DDR3 options
46 and video codec support. Peripherals include Gigabit Ethernet,
47 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
48
Simon Glass2cffe662015-08-30 16:55:38 -060049config ROCKCHIP_RK3288
50 bool "Support Rockchip RK3288"
Andreas Färber6c427032016-07-14 05:09:26 +020051 select CPU_V7
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080052 select SPL_BOARD_INIT if SPL
Kever Yang0d3d7832016-07-19 21:16:59 +080053 select SUPPORT_SPL
54 select SPL
Simon Glass2cffe662015-08-30 16:55:38 -060055 help
56 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
57 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
58 video interfaces supporting HDMI and eDP, several DDR3 options
59 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +010060 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -060061
Kever Yangec02b3c2017-02-23 15:37:51 +080062config ROCKCHIP_RK3328
63 bool "Support Rockchip RK3328"
64 select ARM64
65 help
66 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
67 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
68 video interfaces supporting HDMI and eDP, several DDR3 options
69 and video codec support. Peripherals include Gigabit Ethernet,
70 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
71
Andreas Färber9e3ad682017-05-15 17:51:18 +080072config ROCKCHIP_RK3368
73 bool "Support Rockchip RK3368"
74 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +020075 select SUPPORT_SPL
76 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +020077 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
78 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich84af43e2017-06-11 23:46:25 +020079 imply SPL_SEPARATE_BSS
80 imply SPL_SERIAL_SUPPORT
81 imply TPL_SERIAL_SUPPORT
Philipp Tomsich84af43e2017-06-11 23:46:25 +020082 select DEBUG_UART_BOARD_INIT
Andreas Färber9e3ad682017-05-15 17:51:18 +080083 select SYS_NS16550
84 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +020085 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
86 into a big and little cluster with 4 cores each) Cortex-A53 including
87 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
88 (for the little cluster), PowerVR G6110 based graphics, one video
89 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
90 video codec support.
91
92 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
93 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +080094
Philipp Tomsichcbacb402017-08-02 21:26:18 +020095if ROCKCHIP_RK3368
96
97config TPL_LDSCRIPT
98 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
99
Philipp Tomsich7d1319b2017-07-28 20:20:41 +0200100config TPL_TEXT_BASE
101 default 0xff8c1000
102
103config TPL_MAX_SIZE
104 default 28672
105
106config TPL_STACK
107 default 0xff8cffff
108
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200109endif
110
Kever Yang0d3d7832016-07-19 21:16:59 +0800111config ROCKCHIP_RK3399
112 bool "Support Rockchip RK3399"
113 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800114 select SUPPORT_SPL
115 select SPL
116 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200117 select SPL_SERIAL_SUPPORT
118 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich41029e62017-04-01 12:59:25 +0200119 select DEBUG_UART_BOARD_INIT
Kever Yang0d3d7832016-07-19 21:16:59 +0800120 help
121 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
122 and quad-core Cortex-A53.
123 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
124 video interfaces supporting HDMI and eDP, several DDR3 options
125 and video codec support. Peripherals include Gigabit Ethernet,
126 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
127
Andy Yan2d982da2017-06-01 18:00:55 +0800128config ROCKCHIP_RV1108
129 bool "Support Rockchip RV1108"
130 select CPU_V7
131 help
132 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
133 and a DSP.
134
Philipp Tomsich798370f2017-06-29 11:21:15 +0200135config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800136 bool "SPL returns to bootrom"
137 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100138 select ROCKCHIP_BROM_HELPER
Philipp Tomsich798370f2017-06-29 11:21:15 +0200139 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800140 help
141 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
142 SPL will return to the boot rom, which will then load the U-Boot
143 binary to keep going on.
144
Philipp Tomsich798370f2017-06-29 11:21:15 +0200145config TPL_ROCKCHIP_BACK_TO_BROM
146 bool "TPL returns to bootrom"
147 default y if ROCKCHIP_RK3368
148 select ROCKCHIP_BROM_HELPER
149 depends on TPL
150 help
151 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
152 SPL will return to the boot rom, which will then load the U-Boot
153 binary to keep going on.
154
Kever Yange484f772017-04-20 17:03:46 +0800155config ROCKCHIP_SPL_RESERVE_IRAM
156 hex "Size of IRAM reserved in SPL"
157 default 0x4000
158 help
159 SPL may need reserve memory for firmware loaded by SPL, whose load
160 address is in IRAM and may overlay with SPL text area if not
161 reserved.
162
Heiko Stübner355a8802017-02-18 19:46:25 +0100163config ROCKCHIP_BROM_HELPER
164 bool
165
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200166config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
167 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
168 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
169 help
170 Some Rockchip BROM variants (e.g. on the RK3188) load the
171 first stage in segments and enter multiple times. E.g. on
172 the RK3188, the first 1KB of the first stage are loaded
173 first and entered; after returning to the BROM, the
174 remainder of the first stage is loaded, but the BROM
175 re-enters at the same address/to the same code as previously.
176
177 This enables support code in the BOOT0 hook for the SPL stage
178 to allow multiple entries.
179
180config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
181 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
182 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
183 help
184 Some Rockchip BROM variants (e.g. on the RK3188) load the
185 first stage in segments and enter multiple times. E.g. on
186 the RK3188, the first 1KB of the first stage are loaded
187 first and entered; after returning to the BROM, the
188 remainder of the first stage is loaded, but the BROM
189 re-enters at the same address/to the same code as previously.
190
191 This enables support code in the BOOT0 hook for the TPL stage
192 to allow multiple entries.
193
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400194config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200195 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400196
huang lin1115b642015-11-17 14:20:27 +0800197source "arch/arm/mach-rockchip/rk3036/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100198source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800199source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200200source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800201source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800202source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800203source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800204source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600205endif