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git01.mediatek.com / filogic / uboot / 6fa7ae19bd4e410bfe95b186fbe095a0ec7a3c3e / . / drivers / pinctrl / mediatek / pinctrl-mt7986.c
blob: 449e5adcd9a82c8231ae42ce2125cce8db92fa93 [file] [log] [blame]
developer6fa7ae12022-09-09 19:59:57 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * The MT7986 driver based on Linux generic pinctrl binding.
4 *
5 * Copyright (C) 2022 MediaTek Inc.
6 * Author: Sam Shih <sam.shih@mediatek.com>
7 */
8
9#include <dm.h>
10#include "pinctrl-mtk-common.h"
11
12#define MT7986_TYPE0_PIN(_number, _name) \
13 MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
14
15#define MT7986_TYPE1_PIN(_number, _name) \
16 MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
17
18#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
19 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \
20 _s_bit, _x_bits, 32, 0)
21
22#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
23 _x_bits) \
24 PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
25 _x_bits, 32, 0)
26
27/**
28 * enum - Locking variants of the iocfg bases
29 *
30 * MT7986 have multiple bases to program pin configuration listed as the below:
31 * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
32 * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
33 * _i_based could be used to indicate what base the pin should be mapped into.
34 *
35 * Each iocfg register base control different group of pads on the SoC
36 *
37 *
38 * chip carrier
39 *
40 * A B C D E F G H
41 * +------------------------+
42 * 8 | o o o o o o o o |
43 * 7 | o o o o o o o o |
44 * 6 | o o o o o o o o |
45 * 5 | o o o o o o o o |
46 * 4 | o o o o o o o o |
47 * 3 | o o o o o o o o |
48 * 2 | o o o o o o o o |
49 * 1 | o o o o o o o o |
50 * +------------------------+
51 *
52 * inside Chip carrier
53 *
54 * A B C D E F G H
55 * +------------------------+
56 * 8 | |
57 * 7 | TL TR |
58 * 6 | +---------+ |
59 * 5 | LT | | RT |
60 * 4 | | | |
61 * 3 | LB | | RB |
62 * 2 | +---------+ |
63 * 1 | |
64 * +------------------------+
65 *
66 */
67
68enum {
69 GPIO_BASE,
70 IOCFG_RT_BASE,
71 IOCFG_RB_BASE,
72 IOCFG_LT_BASE,
73 IOCFG_LB_BASE,
74 IOCFG_TR_BASE,
75 IOCFG_TL_BASE,
76};
77
78static const char *const mt7986_pinctrl_register_base_names[] = {
79 "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
80 "iocfg_tl",
81};
82
83static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
84 PIN_FIELD_GPIO(0, 100, 0x300, 0x10, 0, 4),
85};
86
87static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
88 PIN_FIELD_GPIO(0, 100, 0x0, 0x10, 0, 1),
89};
90
91static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
92 PIN_FIELD_GPIO(0, 100, 0x200, 0x10, 0, 1),
93};
94
95static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
96 PIN_FIELD_GPIO(0, 100, 0x100, 0x10, 0, 1),
97};
98
99static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
100 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
101 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
102 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
103 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
104 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
105 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
106 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
107 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
108 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
109 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
110 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
111 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
112 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
113 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
114 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
115 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
116 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
117 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
118 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
119 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
120 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
121 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
122 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
123 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
124 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
125 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
126 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
127 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
128 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
129 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
130 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
131 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
132 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
133 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
134 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
135 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
136 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
137 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
138 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
139 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
140 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
141 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
142 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
143 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
144 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
145 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
146 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
147 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
148 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
149 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
150 PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
151};
152
153static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
154 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
155 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
156 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
157 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
158 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
159 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
160 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
161 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
162 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
163 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
164 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
165 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
166 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
167 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
168 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
169 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
170 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
171 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
172 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
173 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
174 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
175 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
176 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
177 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
178 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
179 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
180 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
181 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
182 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
183 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
184 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
185 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
186 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
187 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
188 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
189 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
190 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
191 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
192 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
193 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
194 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
195 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
196 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
197 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
198 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
199 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
200 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
201 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
202 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
203 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
204 PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
205};
206
207static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
208 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
209 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
210 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
211 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
212 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
213 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
214 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
215 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
216 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
217 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
218 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
219 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
220 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
221 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
222 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
223 PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
224};
225
226static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
227 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
228 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
229 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
230 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
231 PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
232 PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
233 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
234 PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
235 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
236 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
237 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
238 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
239 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
240 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
241 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
242 PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
243};
244
245static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
246 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
247 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
248 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
249 PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
250 PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
251 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
252 PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
253 PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
254 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
255 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
256 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
257 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
258 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
259 PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
260 PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
261 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
262 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
263 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
264 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
265 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
266 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
267 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
268 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
269 PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
270 PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
271 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
272 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
273 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
274 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
275 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
276 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
277 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
278 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
279 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
280 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
281 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
282 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
283 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
284 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
285 PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
286 PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
287 PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
288 PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
289 PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
290 PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
291 PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
292 PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
293 PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
294 PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
295 PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
296 PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
297 PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
298 PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
299 PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
300 PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
301 PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
302};
303
304static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
305 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
306 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
307 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
308 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
309 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
310 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
311 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
312 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
313 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
314 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
315 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
316 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
317 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
318 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
319 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
320 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
321 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
322 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
323 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
324 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
325 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
326 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
327 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
328 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
329 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
330 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
331 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
332 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
333 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
334 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
335 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
336 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
337 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
338 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
339 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
340};
341
342static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
343 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
344 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
345 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
346 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
347 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
348 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
349 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
350 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
351 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
352 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
353 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
354 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
355 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
356 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
357 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
358 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
359 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
360 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
361 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
362 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
363 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
364 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
365 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
366 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
367 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
368 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
369 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
370 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
371 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
372 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
373 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
374 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
375 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
376 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
377 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
378};
379
380static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
381 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
382 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
383 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
384 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
385 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
386 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
387 PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
388 PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
389 PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
390 PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
391 PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
392 PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
393 PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
394 PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
395 PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
396 PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
397 PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
398 PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
399 PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
400 PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
401 PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
402 PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
403 PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
404 PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
405 PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
406 PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
407 PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
408 PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
409 PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
410 PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
411 PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
412 PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
413 PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
414 PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
415 PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
416};
417
418static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
419 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
420 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
421 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
422 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
423 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
424 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
425 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
426 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
427 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
428 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
429 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
430 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
431};
432
433static const struct mtk_pin_desc mt7986_pins[] = {
434 MT7986_TYPE0_PIN(0, "SYS_WATCHDOG"),
435 MT7986_TYPE0_PIN(1, "WF2G_LED"),
436 MT7986_TYPE0_PIN(2, "WF5G_LED"),
437 MT7986_TYPE0_PIN(3, "I2C_SCL"),
438 MT7986_TYPE0_PIN(4, "I2C_SDA"),
439 MT7986_TYPE0_PIN(5, "GPIO_0"),
440 MT7986_TYPE0_PIN(6, "GPIO_1"),
441 MT7986_TYPE0_PIN(7, "GPIO_2"),
442 MT7986_TYPE0_PIN(8, "GPIO_3"),
443 MT7986_TYPE0_PIN(9, "GPIO_4"),
444 MT7986_TYPE0_PIN(10, "GPIO_5"),
445 MT7986_TYPE0_PIN(11, "GPIO_6"),
446 MT7986_TYPE0_PIN(12, "GPIO_7"),
447 MT7986_TYPE0_PIN(13, "GPIO_8"),
448 MT7986_TYPE0_PIN(14, "GPIO_9"),
449 MT7986_TYPE0_PIN(15, "GPIO_10"),
450 MT7986_TYPE0_PIN(16, "GPIO_11"),
451 MT7986_TYPE0_PIN(17, "GPIO_12"),
452 MT7986_TYPE0_PIN(18, "GPIO_13"),
453 MT7986_TYPE0_PIN(19, "GPIO_14"),
454 MT7986_TYPE0_PIN(20, "GPIO_15"),
455 MT7986_TYPE0_PIN(21, "PWM0"),
456 MT7986_TYPE0_PIN(22, "PWM1"),
457 MT7986_TYPE0_PIN(23, "SPI0_CLK"),
458 MT7986_TYPE0_PIN(24, "SPI0_MOSI"),
459 MT7986_TYPE0_PIN(25, "SPI0_MISO"),
460 MT7986_TYPE0_PIN(26, "SPI0_CS"),
461 MT7986_TYPE0_PIN(27, "SPI0_HOLD"),
462 MT7986_TYPE0_PIN(28, "SPI0_WP"),
463 MT7986_TYPE0_PIN(29, "SPI1_CLK"),
464 MT7986_TYPE0_PIN(30, "SPI1_MOSI"),
465 MT7986_TYPE0_PIN(31, "SPI1_MISO"),
466 MT7986_TYPE0_PIN(32, "SPI1_CS"),
467 MT7986_TYPE0_PIN(33, "SPI2_CLK"),
468 MT7986_TYPE0_PIN(34, "SPI2_MOSI"),
469 MT7986_TYPE0_PIN(35, "SPI2_MISO"),
470 MT7986_TYPE0_PIN(36, "SPI2_CS"),
471 MT7986_TYPE0_PIN(37, "SPI2_HOLD"),
472 MT7986_TYPE0_PIN(38, "SPI2_WP"),
473 MT7986_TYPE0_PIN(39, "UART0_RXD"),
474 MT7986_TYPE0_PIN(40, "UART0_TXD"),
475 MT7986_TYPE0_PIN(41, "PCIE_PERESET_N"),
476 MT7986_TYPE0_PIN(42, "UART1_RXD"),
477 MT7986_TYPE0_PIN(43, "UART1_TXD"),
478 MT7986_TYPE0_PIN(44, "UART1_CTS"),
479 MT7986_TYPE0_PIN(45, "UART1_RTS"),
480 MT7986_TYPE0_PIN(46, "UART2_RXD"),
481 MT7986_TYPE0_PIN(47, "UART2_TXD"),
482 MT7986_TYPE0_PIN(48, "UART2_CTS"),
483 MT7986_TYPE0_PIN(49, "UART2_RTS"),
484 MT7986_TYPE0_PIN(50, "EMMC_DATA_0"),
485 MT7986_TYPE0_PIN(51, "EMMC_DATA_1"),
486 MT7986_TYPE0_PIN(52, "EMMC_DATA_2"),
487 MT7986_TYPE0_PIN(53, "EMMC_DATA_3"),
488 MT7986_TYPE0_PIN(54, "EMMC_DATA_4"),
489 MT7986_TYPE0_PIN(55, "EMMC_DATA_5"),
490 MT7986_TYPE0_PIN(56, "EMMC_DATA_6"),
491 MT7986_TYPE0_PIN(57, "EMMC_DATA_7"),
492 MT7986_TYPE0_PIN(58, "EMMC_CMD"),
493 MT7986_TYPE0_PIN(59, "EMMC_CK"),
494 MT7986_TYPE0_PIN(60, "EMMC_DSL"),
495 MT7986_TYPE0_PIN(61, "EMMC_RSTB"),
496 MT7986_TYPE0_PIN(62, "PCM_DTX"),
497 MT7986_TYPE0_PIN(63, "PCM_DRX"),
498 MT7986_TYPE0_PIN(64, "PCM_CLK"),
499 MT7986_TYPE0_PIN(65, "PCM_FS"),
500 MT7986_TYPE0_PIN(66, "MT7531_INT"),
501 MT7986_TYPE0_PIN(67, "SMI_MDC"),
502 MT7986_TYPE0_PIN(68, "SMI_MDIO"),
503 MT7986_TYPE1_PIN(69, "WF0_DIG_RESETB"),
504 MT7986_TYPE1_PIN(70, "WF0_CBA_RESETB"),
505 MT7986_TYPE1_PIN(71, "WF0_XO_REQ"),
506 MT7986_TYPE1_PIN(72, "WF0_TOP_CLK"),
507 MT7986_TYPE1_PIN(73, "WF0_TOP_DATA"),
508 MT7986_TYPE1_PIN(74, "WF0_HB1"),
509 MT7986_TYPE1_PIN(75, "WF0_HB2"),
510 MT7986_TYPE1_PIN(76, "WF0_HB3"),
511 MT7986_TYPE1_PIN(77, "WF0_HB4"),
512 MT7986_TYPE1_PIN(78, "WF0_HB0"),
513 MT7986_TYPE1_PIN(79, "WF0_HB0_B"),
514 MT7986_TYPE1_PIN(80, "WF0_HB5"),
515 MT7986_TYPE1_PIN(81, "WF0_HB6"),
516 MT7986_TYPE1_PIN(82, "WF0_HB7"),
517 MT7986_TYPE1_PIN(83, "WF0_HB8"),
518 MT7986_TYPE1_PIN(84, "WF0_HB9"),
519 MT7986_TYPE1_PIN(85, "WF0_HB10"),
520 MT7986_TYPE1_PIN(86, "WF1_DIG_RESETB"),
521 MT7986_TYPE1_PIN(87, "WF1_CBA_RESETB"),
522 MT7986_TYPE1_PIN(88, "WF1_XO_REQ"),
523 MT7986_TYPE1_PIN(89, "WF1_TOP_CLK"),
524 MT7986_TYPE1_PIN(90, "WF1_TOP_DATA"),
525 MT7986_TYPE1_PIN(91, "WF1_HB1"),
526 MT7986_TYPE1_PIN(92, "WF1_HB2"),
527 MT7986_TYPE1_PIN(93, "WF1_HB3"),
528 MT7986_TYPE1_PIN(94, "WF1_HB4"),
529 MT7986_TYPE1_PIN(95, "WF1_HB0"),
530 MT7986_TYPE1_PIN(96, "WF1_HB0_B"),
531 MT7986_TYPE1_PIN(97, "WF1_HB5"),
532 MT7986_TYPE1_PIN(98, "WF1_HB6"),
533 MT7986_TYPE1_PIN(99, "WF1_HB7"),
534 MT7986_TYPE1_PIN(100, "WF1_HB8"),
535};
536
537static const struct mtk_io_type_desc mt7986_io_type_desc[] = {
538 [IO_TYPE_GRP0] = {
539 .name = "18OD33",
540 .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
541 .drive_set = mtk_pinconf_drive_set_v1,
542 .input_enable = mtk_pinconf_input_enable_v1,
543 },
544 [IO_TYPE_GRP1] = {
545 .name = "18A01",
546 .bias_set = mtk_pinconf_bias_set_pu_pd,
547 .drive_set = mtk_pinconf_drive_set_v1,
548 .input_enable = mtk_pinconf_input_enable_v1,
549 },
550};
551
552/* List all groups consisting of these pins dedicated to the enablement of
553 * certain hardware block and the corresponding mode for all of the pins.
554 * The hardware probably has multiple combinations of these pinouts.
555 */
556
557static int mt7986_watchdog_pins[] = { 0, };
558static int mt7986_watchdog_funcs[] = { 1, };
559
560static int mt7986_wifi_led_pins[] = { 1, 2, };
561static int mt7986_wifi_led_funcs[] = { 1, 1, };
562
563static int mt7986_i2c_pins[] = { 3, 4, };
564static int mt7986_i2c_funcs[] = { 1, 1, };
565
566static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
567static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
568
569static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
570static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
571
572static int mt7986_pwm1_1_pins[] = { 20, };
573static int mt7986_pwm1_1_funcs[] = { 2, };
574
575static int mt7986_pwm0_pins[] = { 21, };
576static int mt7986_pwm0_funcs[] = { 1, };
577
578static int mt7986_pwm1_0_pins[] = { 22, };
579static int mt7986_pwm1_0_funcs[] = { 1, };
580
581static int mt7986_emmc_45_pins[] = {
582 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
583static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
584
585static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
586static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
587
588static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
589static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
590
591static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
592static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
593
594static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
595static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
596
597static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
598static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
599
600static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
601static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
602
603static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
604static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
605
606static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
607static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
608
609static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
610static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
611
612static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
613static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
614
615static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
616static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
617
618static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
619static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
620
621static int mt7986_uart0_pins[] = { 39, 40, };
622static int mt7986_uart0_funcs[] = { 1, 1, };
623
624static int mt7986_pcie_reset_pins[] = { 41, };
625static int mt7986_pcie_reset_funcs[] = { 1, };
626
627static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
628static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
629
630static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
631static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
632
633static int mt7986_emmc_51_pins[] = {
634 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
635static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
636
637static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
638static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
639
640static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
641static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
642
643static int mt7986_switch_int_pins[] = { 66, };
644static int mt7986_switch_int_funcs[] = { 1, };
645
646static int mt7986_mdc_mdio_pins[] = { 67, 68, };
647static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
648
649static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
650static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
651
652static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
653static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
654
655static int mt7986_wf_dbdc_pins[] = {
656 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
657static int mt7986_wf_dbdc_funcs[] = {
658 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
659
660static int mt7986_pcie_clk_pins[] = { 9, };
661static int mt7986_pcie_clk_funcs[] = { 1, };
662
663static int mt7986_pcie_wake_pins[] = { 10, };
664static int mt7986_pcie_wake_funcs[] = { 1, };
665
666static const struct mtk_group_desc mt7986_groups[] = {
667 PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
668 PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
669 PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
670 PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
671 PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
672 PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
673 PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
674 PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
675 PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
676 PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
677 PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
678 PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
679 PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
680 PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
681 PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
682 PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
683 PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
684 PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
685 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
686 PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
687 PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
688 PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
689 PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
690 PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
691 PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
692 PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
693 PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
694 PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
695 PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
696 PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
697 PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
698 PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
699 PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
700 PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
701 PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
702};
703
704/* Joint those groups owning the same capability in user point of view which
705 * allows that people tend to use through the device tree.
706 */
707
708static const char *const mt7986_audio_groups[] = { "pcm", "i2s" };
709static const char *const mt7986_emmc_groups[] = { "emmc_45", "emmc_51", };
710static const char *const mt7986_ethernet_groups[] = { "switch_int",
711 "mdc_mdio", };
712static const char *const mt7986_i2c_groups[] = { "i2c", };
713static const char *const mt7986_led_groups[] = { "wifi_led", };
714static const char *const mt7986_flash_groups[] = { "snfi", };
715static const char *const mt7986_pcie_groups[] = { "pcie_clk", "pcie_wake",
716 "pcie_pereset" };
717static const char *const mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
718static const char *const mt7986_spi_groups[] = { "spi0", "spi0_wp_hold",
719 "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
720static const char *const mt7986_uart_groups[] = { "uart1_0", "uart1_1",
721 "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0", "uart2_1",
722 "uart0", "uart1", "uart2", };
723static const char *const mt7986_wdt_groups[] = { "watchdog", };
724static const char *const mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
725
726static const struct mtk_function_desc mt7986_functions[] = {
727 {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
728 {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
729 {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
730 {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
731 {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
732 {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
733 {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
734 {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
735 {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
736 {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
737 {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
738 {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
739};
740
741static struct mtk_pinctrl_soc mt7986_data = {
742 .name = "mt7986_pinctrl",
743 .reg_cal = mt7986_reg_cals,
744 .pins = mt7986_pins,
745 .npins = ARRAY_SIZE(mt7986_pins),
746 .grps = mt7986_groups,
747 .ngrps = ARRAY_SIZE(mt7986_groups),
748 .funcs = mt7986_functions,
749 .nfuncs = ARRAY_SIZE(mt7986_functions),
750 .io_type = mt7986_io_type_desc,
751 .ntype = ARRAY_SIZE(mt7986_io_type_desc),
752 .gpio_mode = 0,
753 .base_names = mt7986_pinctrl_register_base_names,
754 .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
755 .base_calc = 1,
756};
757
758static int mtk_pinctrl_mt7986_probe(struct udevice *dev)
759{
760 return mtk_pinctrl_common_probe(dev, &mt7986_data);
761}
762
763static const struct udevice_id mt7986_pctrl_match[] = {
764 {.compatible = "mediatek,mt7986-pinctrl"},
765 { /* sentinel */ }
766};
767
768U_BOOT_DRIVER(mt7986_pinctrl) = {
769 .name = "mt7986_pinctrl",
770 .id = UCLASS_PINCTRL,
771 .of_match = mt7986_pctrl_match,
772 .ops = &mtk_pinctrl_ops,
773 .probe = mtk_pinctrl_mt7986_probe,
774 .priv_auto = sizeof(struct mtk_pinctrl_priv),
775};