| Dzmitry Sankouski | 2826cbd | 2021-10-17 13:44:31 +0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Qualcomm SDM845 sysmap |
| 4 | * |
| 5 | * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> |
| 6 | */ |
| 7 | #ifndef _MACH_SYSMAP_SDM845_H |
| 8 | #define _MACH_SYSMAP_SDM845_H |
| 9 | |
| 10 | #define TLMM_BASE_ADDR (0x1010000) |
| 11 | |
| 12 | /* Strength (sdc1) */ |
| 13 | #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) |
| 14 | |
| 15 | /* Clocks: (from CLK_CTL_BASE) */ |
| 16 | #define GPLL0_STATUS (0x0000) |
| 17 | #define APCS_GPLL_ENA_VOTE (0x52000) |
| 18 | #define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) |
| 19 | |
| 20 | #define SDCC2_BCR (0x14000) /* block reset */ |
| 21 | #define SDCC2_APPS_CBCR (0x14004) /* branch control */ |
| 22 | #define SDCC2_AHB_CBCR (0x14008) |
| 23 | #define SDCC2_CMD_RCGR (0x1400c) |
| 24 | #define SDCC2_CFG_RCGR (0x14010) |
| 25 | #define SDCC2_M (0x14014) |
| 26 | #define SDCC2_N (0x14018) |
| 27 | #define SDCC2_D (0x1401C) |
| 28 | |
| 29 | #define RCG2_CFG_REG 0x4 |
| 30 | #define M_REG 0x8 |
| 31 | #define N_REG 0xc |
| 32 | #define D_REG 0x10 |
| 33 | |
| 34 | #define SE9_AHB_CBCR (0x25004) |
| 35 | #define SE9_UART_APPS_CBCR (0x29004) |
| 36 | #define SE9_UART_APPS_CMD_RCGR (0x18148) |
| 37 | #define SE9_UART_APPS_CFG_RCGR (0x1814C) |
| 38 | #define SE9_UART_APPS_M (0x18150) |
| 39 | #define SE9_UART_APPS_N (0x18154) |
| 40 | #define SE9_UART_APPS_D (0x18158) |
| 41 | |
| 42 | #endif |