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git01.mediatek.com / filogic / uboot / 6f88ce235025e8c0c2ac26ab06d79cd5d2e53b32 / . / arch / arm / dts / stm32mp15xx-dhcor-u-boot.dtsi
blob: 804c66283e0809f9ab8fe6b6a8373457a4f1163a [file] [log] [blame]
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright : STMicroelectronics 2018
4 *
5 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]7 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]8 */
9
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]11#include "stm32mp15-u-boot.dtsi"
Marek Vasut272198e2020-04-29 15:08:38 +0200[diff] [blame]12#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
13#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
14#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]15
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]16/ {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-all;
Marek Vasut8b08dfb2021-12-30 23:46:46 +0100[diff] [blame]18
19 aliases {
20 eeprom0 = &eeprom0;
21 };
22
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]23 config {
Marek Vasut39221b52020-04-22 13:18:14 +0200[diff] [blame]24 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]25 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
26 };
27};
28
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]29&flash0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]31};
32
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]33&i2c4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-all;
35 bootph-pre-ram;
Marek Vasut8b08dfb2021-12-30 23:46:46 +0100[diff] [blame]36
37 eeprom0: eeprom@53 {
38 };
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]39};
40
41&i2c4_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]43 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]45 };
46};
47
48&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-all;
50 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]51
52 regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]54 };
55};
56
57&pwr_regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]59};
60
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]61&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]63};
64
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]65&qspi_clk_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]67 pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]69 };
70};
71
72&qspi_bk1_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]74 pins1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]76 };
77 pins2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Marek Vasutc2afb112020-10-01 12:25:55 +0200[diff] [blame]79 };
80};
81
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]82&rcc {
83 st,clksrc = <
84 CLK_MPU_PLL1P
85 CLK_AXI_PLL2P
86 CLK_MCU_PLL3P
87 CLK_PLL12_HSE
88 CLK_PLL3_HSE
89 CLK_PLL4_HSE
90 CLK_RTC_LSE
91 CLK_MCO1_DISABLED
92 CLK_MCO2_DISABLED
93 >;
94
95 st,clkdiv = <
96 1 /*MPU*/
97 0 /*AXI*/
98 0 /*MCU*/
99 1 /*APB1*/
100 1 /*APB2*/
101 1 /*APB3*/
102 1 /*APB4*/
103 2 /*APB5*/
104 23 /*RTC*/
105 0 /*MCO1*/
106 0 /*MCO2*/
107 >;
108
109 st,pkcs = <
110 CLK_CKPER_HSE
111 CLK_FMC_ACLK
112 CLK_QSPI_ACLK
113 CLK_ETH_DISABLED
114 CLK_SDMMC12_PLL4P
115 CLK_DSI_DSIPLL
116 CLK_STGEN_HSE
117 CLK_USBPHY_HSE
118 CLK_SPI2S1_PLL3Q
119 CLK_SPI2S23_PLL3Q
120 CLK_SPI45_HSI
121 CLK_SPI6_HSI
122 CLK_I2C46_HSI
123 CLK_SDMMC3_PLL4P
124 CLK_USBO_USBPHY
125 CLK_ADC_CKPER
126 CLK_CEC_LSE
127 CLK_I2C12_HSI
128 CLK_I2C35_HSI
129 CLK_UART1_HSI
130 CLK_UART24_HSI
131 CLK_UART35_HSI
132 CLK_UART6_HSI
133 CLK_UART78_HSI
134 CLK_SPDIF_PLL4P
Antonio Borneo84159e82020-01-28 10:11:01 +0100[diff] [blame]135 CLK_FDCAN_PLL4R
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]136 CLK_SAI1_PLL3Q
137 CLK_SAI2_PLL3Q
138 CLK_SAI3_PLL3Q
139 CLK_SAI4_PLL3Q
140 CLK_RNG1_LSI
141 CLK_RNG2_LSI
142 CLK_LPTIM1_PCLK1
143 CLK_LPTIM23_PCLK3
144 CLK_LPTIM45_LSE
145 >;
146
Marek Vasut086fa932022-10-11 22:42:44 +0200[diff] [blame]147 /*
148 * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
149 * frac = < f >;
150 *
151 * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
152 * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
153 * m ... for PLL1,2: m=2 ; for PLL3,4: m=1
154 * XTAL = 24 MHz
155 *
156 * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
157 * P = VCO / (P + 1)
158 * Q = VCO / (Q + 1)
159 * R = VCO / (R + 1)
160 */
161
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]162 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
163 pll2: st,pll@1 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]164 compatible = "st,stm32mp1-pll";
165 reg = <1>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]166 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
167 frac = < 0x1400 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]168 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]169 };
170
171 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
172 pll3: st,pll@2 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]173 compatible = "st,stm32mp1-pll";
174 reg = <2>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]175 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
176 frac = < 0x1a04 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]177 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]178 };
179
Marek Vasut086fa932022-10-11 22:42:44 +0200[diff] [blame]180 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]181 pll4: st,pll@3 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]182 compatible = "st,stm32mp1-pll";
183 reg = <3>;
Marek Vasutb48223e2020-08-22 22:45:25 +0200[diff] [blame]184 cfg = < 3 98 5 7 5 PQR(1,1,1) >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]185 bootph-all;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]186 };
187};
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]188
189&reg11 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]190 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]191};
192
193&reg18 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]194 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]195};
196
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]197&usb33 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]198 bootph-pre-ram;
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]199};
200
201&usbotg_hs_pins_a {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]202 bootph-pre-ram;
Marek Vasut5c92da92022-01-28 19:35:20 +0100[diff] [blame]203};
204
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]205&usbotg_hs {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]206 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]207};
208
209&usbphyc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]210 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]211};
212
213&usbphyc_port0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]214 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]215};
216
217&usbphyc_port1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]218 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]219};
220
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]221&vdd_usb {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]222 bootph-pre-ram;
Marek Vasutacb41692021-12-06 21:58:09 +0100[diff] [blame]223};