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git01.mediatek.com / filogic / uboot / 6f88ce235025e8c0c2ac26ab06d79cd5d2e53b32 / . / arch / arm / dts / k3-am68-sk-base-board-u-boot.dtsi
blob: ee31b1ebe7ca40531644cfbdc4c58bbf4cff1ba0 [file] [log] [blame]
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/ {
7 chosen {
8 stdout-path = "serial2:115200n8";
9 tick-timer = &timer1;
10 };
11
12 aliases {
13 serial0 = &wkup_uart0;
14 serial1 = &mcu_uart0;
15 serial2 = &main_uart8;
16 i2c0 = &wkup_i2c0;
17 i2c1 = &mcu_i2c0;
18 i2c2 = &mcu_i2c1;
19 i2c3 = &main_i2c0;
20 ethernet0 = &cpsw_port1;
21 mmc1 = &main_sdhci1;
22 };
23};
24
25&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]27};
28
29&cbass_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]31};
32
33&main_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]35};
36
37&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]39
40 timer1: timer@40400000 {
41 compatible = "ti,omap5430-timer";
42 reg = <0x0 0x40400000 0x0 0x80>;
43 ti,timer-alwon;
44 clock-frequency = <250000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]46 };
47
48 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]50 };
51};
52
53&mcu_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]55};
56
57&mcu_ringacc {
58 reg = <0x0 0x2b800000 0x0 0x400000>,
59 <0x0 0x2b000000 0x0 0x400000>,
60 <0x0 0x28590000 0x0 0x100>,
61 <0x0 0x2a500000 0x0 0x40000>,
62 <0x0 0x28440000 0x0 0x40000>;
63 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]65};
66
67&mcu_udmap {
68 reg = <0x0 0x285c0000 0x0 0x100>,
69 <0x0 0x284c0000 0x0 0x4000>,
70 <0x0 0x2a800000 0x0 0x40000>,
71 <0x0 0x284a0000 0x0 0x4000>,
72 <0x0 0x2aa00000 0x0 0x40000>,
73 <0x0 0x28400000 0x0 0x2000>;
74 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
75 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]77};
78
79&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]81};
82
83&sms {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]85 k3_sysreset: sysreset-controller {
86 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]88 };
89};
90
91&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]93};
94
95&main_uart8_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]97};
98
99&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]101};
102
103&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]105};
106
107&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]109};
110
111&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]113};
114
115&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]117};
118
119&main_uart8 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]121};
122
123&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]125};
126
127&wkup_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]129};
130
131&mcu_cpsw {
132 reg = <0x0 0x46000000 0x0 0x200000>,
133 <0x0 0x40f00200 0x0 0x8>;
134 reg-names = "cpsw_nuss", "mac_efuse";
135 /delete-property/ ranges;
136
137 cpsw-phy-sel@40f04040 {
138 compatible = "ti,am654-cpsw-phy-sel";
139 reg= <0x0 0x40f04040 0x0 0x4>;
140 reg-names = "gmii-sel";
141 };
142};
143
144&main_sdhci0 {
145 status = "disabled";
146};
147
148&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]149 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]150};