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git01.mediatek.com / filogic / uboot / 6f608023720e9207aa1481207ef39d315adf722e / . / board / mpr2 / mpr2.c
blob: 488185943f476d53cda5d58824a61589f5df20f4 [file] [log] [blame]
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]1/*
2 * Copyright (C) 2008
3 * Mark Jonas <mark.jonas@de.bosch.com>
4 *
5 * board/mpr2/mpr2.c
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/io.h>
25#include <asm/processor.h>
26
John Rigby0d21ed02010-12-20 18:27:51 -0700[diff] [blame]27DECLARE_GLOBAL_DATA_PTR;
28
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]29int checkboard(void)
30{
31 puts("BOARD: MPR2\n");
32 return 0;
33}
34
35int board_init(void)
36{
37 /*
38 * For MPR2 A.3 through A.7
39 */
40
41 /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
42 __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */
43 __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */
44
45 /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
46 __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */
47 __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
48
49 /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
50 __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */
51 __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
52
53 /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
54 __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */
55 __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
56
57 /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
58 __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */
59 __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
60
61 /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
62 __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */
63
64 /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
65 __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */
66
67 /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
68 __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */
69
70 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
71 __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
Wolfgang Denk35f734f2008-04-13 09:59:26 -0700[diff] [blame]72
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]73 /* OTH: (00) Other fuction
74 * GPO: (01) General Purpose Output
75 * GPI: (11) General Purpose Input
76 * GPI+: (10) General Purpose Input with internal pull-up
77 *-------------------------------------------------------
78 * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
79 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */
80 __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */
81
82 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
83 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */
84 __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */
85
86 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
87 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */
88 __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */
89
90 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
91 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */
92 __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */
93
94 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
95 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */
96 __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */
97
98 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
99 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */
100 __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */
101
102 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
103 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */
104 __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */
105
106 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
107 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */
108 __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */
109
110 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
111 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */
112 __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */
113
114 /* K7 (x); K6 (x); K5 (x); K4 (x)
115 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */
116 __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */
117
118 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
119 * L3 TCK; L2 (x); L1 (x); L0 (x); */
120 __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */
121
122 /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET);
123 * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */
124 __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */
125 __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
126
127 /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup);
128 * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */
129 __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */
130 __raw_writeb(0x10, PPDR); /* no current flow through pullup */
131
132 /* R7 A25; R6 A24; R5 A23; R4 A22;
133 * R3 A21; R2 A20; R1 A19; R0 A0; */
134 __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */
135
136 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
137 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */
138 __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */
139
140 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
141 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */
142 __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */
143
144 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
145 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */
146 __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */
147
148 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
149 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */
150 __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */
151
152 return 0;
153}
154
155int dram_init(void)
156{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]157 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
158 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
159 printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]160 return 0;
161}