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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wenyou Yang5a09d132015-11-04 14:25:13 +08002/*
3 * Copyright (C) 2015 Atmel Corporation.
4 * Wenyou Yang <wenyou.yang@atmel.com>
Wenyou Yang5a09d132015-11-04 14:25:13 +08005 */
6
7#ifndef __ATMEL_PIO4_H
8#define __ATMEL_PIO4_H
9
10#ifndef __ASSEMBLY__
11
Simon Glass4dcacfc2020-05-10 11:40:13 -060012#include <linux/bitops.h>
Wenyou Yang5a09d132015-11-04 14:25:13 +080013struct atmel_pio4_port {
14 u32 mskr; /* 0x00 PIO Mask Register */
15 u32 cfgr; /* 0x04 PIO Configuration Register */
16 u32 pdsr; /* 0x08 PIO Pin Data Status Register */
17 u32 locksr; /* 0x0C PIO Lock Status Register */
18 u32 sodr; /* 0x10 PIO Set Output Data Register */
19 u32 codr; /* 0x14 PIO Clear Output Data Register */
20 u32 odsr; /* 0x18 PIO Output Data Status Register */
21 u32 reserved0;
22 u32 ier; /* 0x20 PIO Interrupt Enable Register */
23 u32 idr; /* 0x24 PIO Interrupt Disable Register */
24 u32 imr; /* 0x28 PIO Interrupt Mask Register */
25 u32 isr; /* 0x2C PIO Interrupt Status Register */
26 u32 reserved1[3];
27 u32 iofr; /* 0x3C PIO I/O Freeze Register */
28};
29
30#endif
31
Wenyou Yang312bf892016-07-20 17:16:25 +080032/*
33 * PIO Configuration Register Fields
34 */
35#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
36#define ATMEL_PIO_CFGR_FUNC_GPIO (0x0 << 0)
37#define ATMEL_PIO_CFGR_FUNC_PERIPH_A (0x1 << 0)
38#define ATMEL_PIO_CFGR_FUNC_PERIPH_B (0x2 << 0)
39#define ATMEL_PIO_CFGR_FUNC_PERIPH_C (0x3 << 0)
40#define ATMEL_PIO_CFGR_FUNC_PERIPH_D (0x4 << 0)
41#define ATMEL_PIO_CFGR_FUNC_PERIPH_E (0x5 << 0)
42#define ATMEL_PIO_CFGR_FUNC_PERIPH_F (0x6 << 0)
43#define ATMEL_PIO_CFGR_FUNC_PERIPH_G (0x7 << 0)
44#define ATMEL_PIO_DIR_MASK BIT(8)
45#define ATMEL_PIO_PUEN_MASK BIT(9)
46#define ATMEL_PIO_PDEN_MASK BIT(10)
47#define ATMEL_PIO_IFEN_MASK BIT(12)
48#define ATMEL_PIO_IFSCEN_MASK BIT(13)
49#define ATMEL_PIO_OPD_MASK BIT(14)
50#define ATMEL_PIO_SCHMITT_MASK BIT(15)
Ludovic Desroches1103e0d2018-04-23 10:59:49 +030051#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
52#define ATMEL_PIO_DRVSTR_LO (1 << 16)
53#define ATMEL_PIO_DRVSTR_ME (2 << 16)
54#define ATMEL_PIO_DRVSTR_HI (3 << 16)
Eugen Hristev90add2b2021-01-05 10:54:01 +020055#define ATMEL_PIO_DRVSTR_OFFSET 16
Wenyou Yang312bf892016-07-20 17:16:25 +080056#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
57#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
58#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
59#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
60#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
61#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
62
63#define ATMEL_PIO_NPINS_PER_BANK 32
64#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
65#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
66#define ATMEL_PIO_BANK_OFFSET 0x40
67
68#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
69#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
70#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
71
Wenyou Yang5a09d132015-11-04 14:25:13 +080072#define AT91_PIO_PORTA 0x0
73#define AT91_PIO_PORTB 0x1
74#define AT91_PIO_PORTC 0x2
75#define AT91_PIO_PORTD 0x3
76
Ludovic Desroches86504912018-04-24 10:16:01 +030077int atmel_pio4_set_gpio(u32 port, u32 pin, u32 config);
78int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 config);
79int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 config);
80int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 config);
81int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 config);
82int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 config);
83int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 config);
84int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 config);
Wenyou Yang5a09d132015-11-04 14:25:13 +080085int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value);
86int atmel_pio4_get_pio_input(u32 port, u32 pin);
87
88#endif