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git01.mediatek.com / filogic / uboot / 6f024c91b1f8e3f0ae24ec6c1f33537adf6274ad / . / arch / powerpc / cpu / mpc85xx / bsc9132_serdes.c
blob: 300a4dbcf659b08fab22833d1bab80a8bd1cc043 [file] [log] [blame]
Prabhakar Kushwaha92543c22013-01-23 17:59:57 +0000[diff] [blame]1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or (at your option)
8 * any later version.
9 */
10
11#include <config.h>
12#include <common.h>
13#include <asm/io.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_serdes.h>
16
17#define SRDS1_MAX_LANES 4
18
19static u32 serdes1_prtcl_map;
20
21static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
22 [0] = {NONE, NONE, NONE, NONE},
23 [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
24 [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
25 [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
26 [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
27 [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
28 [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
29 [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
30 [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
31 [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
32 [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
33 [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
34 [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
35 [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
36 [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
37 [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
38 [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
39 [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
40 [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
41 [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
42 [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
43 [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
44 [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
45 [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
46 [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
47 [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
48 [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
49 [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
50 [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
51 [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
52 [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
53 [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
54 [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
55 [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
56 [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
57 [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
58 [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
59 [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
60 [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
61 [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
62 [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
63 [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
64 [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
65 [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
66 [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
67 [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
68 [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
69 [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
70};
71
72int is_serdes_configured(enum srds_prtcl prtcl)
73{
74 return (1 << prtcl) & serdes1_prtcl_map;
75}
76
77void fsl_serdes_init(void)
78{
79 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
80 u32 pordevsr = in_be32(&gur->pordevsr);
81 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
82 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
83 int lane;
84
85 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
86
87 if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
88 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
89 return;
90 }
91
92 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
93 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
94 serdes1_prtcl_map |= (1 << lane_prtcl);
95 }
96}