| Vitaly Andrianov | 7bcf4d6 | 2014-04-04 13:16:53 -0400 | [diff] [blame] | 1 | /* |
| 2 | * emif definitions to re-use davinci emif driver on Keystone2 |
| 3 | * |
| 4 | * (C) Copyright 2012-2014 |
| 5 | * Texas Instruments Incorporated, <www.ti.com> |
| 6 | * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net> |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | #ifndef _EMIF_DEFS_H_ |
| 11 | #define _EMIF_DEFS_H_ |
| 12 | |
| 13 | #include <asm/arch/hardware.h> |
| 14 | |
| 15 | struct davinci_emif_regs { |
| 16 | uint32_t ercsr; |
| 17 | uint32_t awccr; |
| 18 | uint32_t sdbcr; |
| 19 | uint32_t sdrcr; |
| 20 | uint32_t abncr[4]; |
| 21 | uint32_t sdtimr; |
| 22 | uint32_t ddrsr; |
| 23 | uint32_t ddrphycr; |
| 24 | uint32_t ddrphysr; |
| 25 | uint32_t totar; |
| 26 | uint32_t totactr; |
| 27 | uint32_t ddrphyid_rev; |
| 28 | uint32_t sdsretr; |
| 29 | uint32_t eirr; |
| 30 | uint32_t eimr; |
| 31 | uint32_t eimsr; |
| 32 | uint32_t eimcr; |
| 33 | uint32_t ioctrlr; |
| 34 | uint32_t iostatr; |
| 35 | uint32_t rsvd0; |
| 36 | uint32_t one_nand_cr; |
| 37 | uint32_t nandfcr; |
| 38 | uint32_t nandfsr; |
| 39 | uint32_t rsvd1[2]; |
| 40 | uint32_t nandfecc[4]; |
| 41 | uint32_t rsvd2[15]; |
| 42 | uint32_t nand4biteccload; |
| 43 | uint32_t nand4bitecc[4]; |
| 44 | uint32_t nanderradd1; |
| 45 | uint32_t nanderradd2; |
| 46 | uint32_t nanderrval1; |
| 47 | uint32_t nanderrval2; |
| 48 | }; |
| 49 | |
| 50 | #define davinci_emif_regs \ |
| 51 | ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) |
| 52 | |
| 53 | #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) |
| 54 | #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) |
| 55 | #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) |
| 56 | #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) |
| 57 | #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) |
| 58 | #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) |
| 59 | |
| 60 | /* Chip Select setup */ |
| 61 | #define DAVINCI_ABCR_STROBE_SELECT (1 << 31) |
| 62 | #define DAVINCI_ABCR_EXT_WAIT (1 << 30) |
| 63 | #define DAVINCI_ABCR_WSETUP(n) ((n) << 26) |
| 64 | #define DAVINCI_ABCR_WSTROBE(n) ((n) << 20) |
| 65 | #define DAVINCI_ABCR_WHOLD(n) ((n) << 17) |
| 66 | #define DAVINCI_ABCR_RSETUP(n) ((n) << 13) |
| 67 | #define DAVINCI_ABCR_RSTROBE(n) ((n) << 7) |
| 68 | #define DAVINCI_ABCR_RHOLD(n) ((n) << 4) |
| 69 | #define DAVINCI_ABCR_TA(n) ((n) << 2) |
| 70 | #define DAVINCI_ABCR_ASIZE_16BIT 1 |
| 71 | #define DAVINCI_ABCR_ASIZE_8BIT 0 |
| 72 | |
| 73 | #endif |