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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Felix Brack1ba8c9e2018-01-23 18:27:22 +01002/*
3 * board.c
4 *
5 * Board functions for EETS PDU001 board
6 *
7 * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
8 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -05009 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
Felix Brack1ba8c9e2018-01-23 18:27:22 +010010 */
11
Tom Riniffcde002024-04-30 20:41:39 -060012#include <config.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060013#include <env.h>
Felix Brack1ba8c9e2018-01-23 18:27:22 +010014#include <errno.h>
Simon Glassa7b51302019-11-14 12:57:46 -070015#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
Felix Brack1ba8c9e2018-01-23 18:27:22 +010017#include <spl.h>
18#include <i2c.h>
Felix Brack1ba8c9e2018-01-23 18:27:22 +010019#include <watchdog.h>
20#include <debug_uart.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060021#include <asm/global_data.h>
Felix Brack1ba8c9e2018-01-23 18:27:22 +010022#include <dm/ofnode.h>
23#include <power/pmic.h>
24#include <power/regulator.h>
25#include <asm/arch/cpu.h>
26#include <asm/arch/hardware.h>
27#include <asm/arch/omap.h>
28#include <asm/arch/ddr_defs.h>
29#include <asm/arch/clock.h>
30#include <asm/arch/gpio.h>
31#include <asm/arch/mmc_host_def.h>
32#include <asm/arch/sys_proto.h>
33#include <asm/arch/mem.h>
34#include <asm/io.h>
35#include <asm/emif.h>
36#include <asm/gpio.h>
37#include "board.h"
38
39DECLARE_GLOBAL_DATA_PTR;
40
41#define I2C_ADDR_NODE_ID 0x50
42#define I2C_REG_NODE_ID_BASE 0xfa
43#define NODE_ID_BYTE_COUNT 6
44
45#define I2C_ADDR_LEDS 0x60
46#define I2C_REG_RUN_LED 0x06
47#define RUN_LED_OFF 0x0
48#define RUN_LED_RED 0x1
49#define RUN_LED_GREEN (0x1 << 2)
50
51#define VDD_MPU_REGULATOR "regulator@2"
52#define VDD_CORE_REGULATOR "regulator@3"
53#define DEFAULT_CORE_VOLTAGE 1137500
54
55/*
56 * boot device save register
57 * -------------------------
58 * The boot device can be quired by 'spl_boot_device()' in
59 * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
60 * environment here. In turn 'spl_boot_device' can't be called in
61 * 'board_late_init' which allows writing to u-boot environment.
62 * To get the boot device from 'am33xx_spl_board_init' to
63 * 'board_late_init' we therefore use a scratch register from the RTC.
64 */
Tom Rini364d0022023-01-10 11:19:45 -050065#define CFG_SYS_RTC_SCRATCH0 0x60
66#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CFG_SYS_RTC_SCRATCH0)
Felix Brack1ba8c9e2018-01-23 18:27:22 +010067
68#ifdef CONFIG_SPL_BUILD
69static void save_boot_device(void)
70{
71 *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
72}
73#endif
74
75u32 boot_device(void)
76{
77 return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
78}
79
80/* Store the boot device in the environment variable 'boot_device' */
81static void env_set_boot_device(void)
82{
83 switch (boot_device()) {
84 case BOOT_DEVICE_MMC1: {
85 env_set("boot_device", "emmc");
86 break;
87 }
88 case BOOT_DEVICE_MMC2: {
89 env_set("boot_device", "sdcard");
90 break;
91 }
92 default: {
93 env_set("boot_device", "unknown");
94 break;
95 }
96 }
97}
98
99static void set_run_led(struct udevice *dev)
100{
101 int val = RUN_LED_OFF;
102
103 if (IS_ENABLED(CONFIG_RUN_LED_RED))
104 val = RUN_LED_RED;
105 else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
106 val = RUN_LED_GREEN;
107
108 dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
109}
110
111/* Set 'serial#' to the EUI-48 value of board node ID chip */
112static void env_set_serial(struct udevice *dev)
113{
114 int val;
115 char serial[2 * NODE_ID_BYTE_COUNT + 1];
116 int n;
117
118 for (n = 0; n < sizeof(serial); n += 2) {
119 val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
120 sprintf(serial + n, "%02X", val);
121 }
122 serial[2 * NODE_ID_BYTE_COUNT] = '\0';
123 env_set("serial#", serial);
124}
125
126static void set_mpu_and_core_voltage(void)
127{
128 int mpu_vdd;
129 int sil_rev;
130 struct udevice *dev;
131 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
132
133 /*
134 * The PDU001 (more precisely the computing module m2) uses a
135 * TPS65910 PMIC. For all MPU frequencies we support we use a CORE
136 * voltage of 1.1375V. For MPU voltage we need to switch based on
137 * the frequency we are running at.
138 */
139
140 /*
141 * Depending on MPU clock and PG we will need a different VDD
142 * to drive at that speed.
143 */
144 sil_rev = readl(&cdev->deviceid) >> 28;
145 mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
146
147 /* first update the MPU voltage */
148 if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
149 if (regulator_set_value(dev, mpu_vdd))
150 debug("failed to set MPU voltage\n");
151 } else {
152 debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
153 }
154
155 /* second update the CORE voltage */
156 if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
157 if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
158 debug("failed to set CORE voltage\n");
159 } else {
160 debug("invalid CORE voltage ragulator %s\n",
161 VDD_CORE_REGULATOR);
162 }
163}
164
Tom Rinie1e85442021-08-27 21:18:30 -0400165#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Felix Brack1ba8c9e2018-01-23 18:27:22 +0100166static const struct ddr_data ddr2_data = {
167 .datardsratio0 = MT47H128M16RT25E_RD_DQS,
168 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
169 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
170};
171
172static const struct cmd_control ddr2_cmd_ctrl_data = {
173 .cmd0csratio = MT47H128M16RT25E_RATIO,
174 .cmd1csratio = MT47H128M16RT25E_RATIO,
175 .cmd2csratio = MT47H128M16RT25E_RATIO,
176};
177
178static const struct emif_regs ddr2_emif_reg_data = {
179 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
180 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
181 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
182 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
183 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
184 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
185};
186
187#define OSC (V_OSCK / 1000000)
188const struct dpll_params dpll_ddr = {
189 266, OSC - 1, 1, -1, -1, -1, -1};
190const struct dpll_params dpll_ddr_evm_sk = {
191 303, OSC - 1, 1, -1, -1, -1, -1};
192const struct dpll_params dpll_ddr_bone_black = {
193 400, OSC - 1, 1, -1, -1, -1, -1};
194
195void am33xx_spl_board_init(void)
196{
197 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
198
199 /* Get the frequency */
200 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
201
202 /* Set CORE Frequencies to OPP100 */
203 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
204
205 /* Set MPU Frequency to what we detected now that voltages are set */
206 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
207
208 /* save boot device for later use by 'board_late_init' */
209 save_boot_device();
210}
211
212const struct dpll_params *get_dpll_ddr_params(void)
213{
214 enable_i2c0_pin_mux();
Felix Brack1ba8c9e2018-01-23 18:27:22 +0100215
216 return &dpll_ddr;
217}
218
Felix Brackddd82712022-02-21 14:26:05 +0100219void set_uart_mux_conf(void)
220{
221 switch (CONFIG_CONS_INDEX) {
222 case 1: {
223 enable_uart0_pin_mux();
224 break;
225 }
226 case 2: {
227 enable_uart1_pin_mux();
228 break;
229 }
230 case 3: {
231 enable_uart2_pin_mux();
232 break;
233 }
234 case 4: {
235 enable_uart3_pin_mux();
236 break;
237 }
238 case 5: {
239 enable_uart4_pin_mux();
240 break;
241 }
242 case 6: {
243 enable_uart5_pin_mux();
244 break;
245 }
246 }
247}
248
Felix Brack1ba8c9e2018-01-23 18:27:22 +0100249void set_mux_conf_regs(void)
250{
251 /* done first by the ROM and afterwards by the pin controller driver */
252 enable_i2c0_pin_mux();
253}
254
255const struct ctrl_ioregs ioregs = {
256 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
257 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
258 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
259 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
260 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
261};
262
263void sdram_init(void)
264{
265 config_ddr(266, &ioregs, &ddr2_data,
266 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
267}
Tom Rinie1e85442021-08-27 21:18:30 -0400268#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
Felix Brack1ba8c9e2018-01-23 18:27:22 +0100269
270#ifdef CONFIG_DEBUG_UART
271void board_debug_uart_init(void)
272{
Felix Brackc72972c2022-02-15 15:27:23 +0100273 setup_early_clocks();
274
Felix Brack1ba8c9e2018-01-23 18:27:22 +0100275 /* done by pin controller driver if not debugging */
Pali Rohár8864b352022-05-27 22:15:24 +0200276 enable_uart_pin_mux(CONFIG_VAL(DEBUG_UART_BASE));
Felix Brack1ba8c9e2018-01-23 18:27:22 +0100277}
278#endif
279
280/*
281 * Basic board specific setup. Pinmux has been handled already.
282 */
283int board_init(void)
284{
285#ifdef CONFIG_HW_WATCHDOG
286 hw_watchdog_init();
287#endif
288
Tom Rinibb4dd962022-11-16 13:10:37 -0500289 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
Felix Brack1ba8c9e2018-01-23 18:27:22 +0100290 return 0;
291}
292
293#ifdef CONFIG_BOARD_LATE_INIT
294int board_late_init(void)
295{
296 struct udevice *dev;
297
298 set_mpu_and_core_voltage();
299 env_set_boot_device();
300
301 /* second I2C bus connects to node ID and front panel LED chip */
302 if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
303 set_run_led(dev);
304 if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
305 env_set_serial(dev);
306
307 return 0;
308}
309#endif