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Stefan Roesefdf21b12007-03-21 13:39:57 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesefdf21b12007-03-21 13:39:57 +01006 */
7
Stefan Roesef6c7b762007-03-24 15:45:34 +01008/* define DEBUG for debugging output (obviously ;-)) */
9#if 0
10#define DEBUG
11#endif
12
Stefan Roesefdf21b12007-03-21 13:39:57 +010013#include <common.h>
14#include <asm/processor.h>
Stefan Roesef6c7b762007-03-24 15:45:34 +010015#include <asm/io.h>
Stefan Roesede21eab2010-09-16 14:30:37 +020016#include <asm/ppc4xx-gpio.h>
Stefan Roesefdf21b12007-03-21 13:39:57 +010017
Simon Glass39f90ba2017-03-31 08:40:25 -060018DECLARE_GLOBAL_DATA_PTR;
19
Stefan Roese80d99a42007-06-19 16:42:31 +020020extern void board_pll_init_f(void);
21
Stefan Roesefdf21b12007-03-21 13:39:57 +010022static void cram_bcr_write(u32 wr_val)
23{
Stefan Roesef6c7b762007-03-24 15:45:34 +010024 wr_val <<= 2;
Stefan Roesefdf21b12007-03-21 13:39:57 +010025
Stefan Roesef6c7b762007-03-24 15:45:34 +010026 /* set CRAM_CRE to 1 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020027 gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
Stefan Roesefdf21b12007-03-21 13:39:57 +010028
Stefan Roesef6c7b762007-03-24 15:45:34 +010029 /* Write BCR to CRAM on CS1 */
30 out32(wr_val + 0x00200000, 0);
31 debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
Stefan Roesefdf21b12007-03-21 13:39:57 +010032
Stefan Roesef6c7b762007-03-24 15:45:34 +010033 /* Write BCR to CRAM on CS2 */
34 out32(wr_val + 0x02200000, 0);
35 debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
Stefan Roesefdf21b12007-03-21 13:39:57 +010036
Stefan Roesef6c7b762007-03-24 15:45:34 +010037 sync();
38 eieio();
Stefan Roesefdf21b12007-03-21 13:39:57 +010039
Stefan Roesef6c7b762007-03-24 15:45:34 +010040 /* set CRAM_CRE back to 0 (normal operation) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041 gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
Stefan Roesefdf21b12007-03-21 13:39:57 +010042
Stefan Roesefdf21b12007-03-21 13:39:57 +010043 return;
44}
45
Simon Glassd35f3382017-04-06 12:47:05 -060046int dram_init(void)
Stefan Roesefdf21b12007-03-21 13:39:57 +010047{
Stefan Roese23d8d342007-06-06 11:42:13 +020048 int i;
Stefan Roesef6c7b762007-03-24 15:45:34 +010049 u32 val;
Stefan Roesefdf21b12007-03-21 13:39:57 +010050
Stefan Roesef6c7b762007-03-24 15:45:34 +010051 /* 1. EBC need to program READY, CLK, ADV for ASync mode */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052 gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
53 gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
54 gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
55 gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
Stefan Roesefdf21b12007-03-21 13:39:57 +010056
Stefan Roesef6c7b762007-03-24 15:45:34 +010057 /* 2. EBC in Async mode */
Stefan Roese918010a2009-09-09 16:25:29 +020058 mtebc(PB1AP, 0x078F1EC0);
59 mtebc(PB2AP, 0x078F1EC0);
60 mtebc(PB1CR, 0x000BC000);
61 mtebc(PB2CR, 0x020BC000);
Stefan Roesefdf21b12007-03-21 13:39:57 +010062
Stefan Roesef6c7b762007-03-24 15:45:34 +010063 /* 3. Set CRAM in Sync mode */
64 cram_bcr_write(0x7012); /* CRAM burst setting */
Stefan Roesefdf21b12007-03-21 13:39:57 +010065
Stefan Roesef6c7b762007-03-24 15:45:34 +010066 /* 4. EBC in Sync mode */
Stefan Roese918010a2009-09-09 16:25:29 +020067 mtebc(PB1AP, 0x9C0201C0);
68 mtebc(PB2AP, 0x9C0201C0);
Stefan Roesefdf21b12007-03-21 13:39:57 +010069
Stefan Roesef6c7b762007-03-24 15:45:34 +010070 /* Set GPIO pins back to alternate function */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071 gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
72 gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
Stefan Roesefdf21b12007-03-21 13:39:57 +010073
Stefan Roesef6c7b762007-03-24 15:45:34 +010074 /* Config EBC to use RDY */
Stefan Roese918010a2009-09-09 16:25:29 +020075 mfsdr(SDR0_ULTRA0, val);
76 mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
Stefan Roese23d8d342007-06-06 11:42:13 +020077
78 /* Wait a short while, since for NAND booting this is too fast */
79 for (i=0; i<200000; i++)
80 ;
Stefan Roesefdf21b12007-03-21 13:39:57 +010081
Simon Glass39f90ba2017-03-31 08:40:25 -060082 gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20;
83
84 return 0;
Stefan Roesefdf21b12007-03-21 13:39:57 +010085}