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Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09001/*
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +09002 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
Masahiro Yamada5e05c4d2017-06-22 16:42:04 +090010#include <fdt_support.h>
Masahiro Yamada1f752802016-04-21 14:43:12 +090011#include <fdtdec.h>
Masahiro Yamadae4e789d2017-01-21 18:05:24 +090012#include <linux/errno.h>
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +090013#include <linux/sizes.h>
Masahiro Yamadab4782cd2015-09-11 20:17:49 +090014
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +090015#include "sg-regs.h"
Masahiro Yamada460483c2016-06-17 19:24:29 +090016#include "soc-info.h"
17
Masahiro Yamada3dc80972017-02-05 10:52:12 +090018#define pr_warn(fmt, args...) printf(fmt, ##args)
19#define pr_err(fmt, args...) printf(fmt, ##args)
20
Masahiro Yamadab4782cd2015-09-11 20:17:49 +090021DECLARE_GLOBAL_DATA_PTR;
22
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +090023struct uniphier_memif_data {
24 unsigned int soc_id;
25 unsigned long sparse_ch1_base;
26 int have_ch2;
27};
28
29static const struct uniphier_memif_data uniphier_memif_data[] = {
30 {
31 .soc_id = UNIPHIER_SLD3_ID,
32 .sparse_ch1_base = 0xc0000000,
33 /*
34 * In fact, SLD3 has DRAM ch2, but the memory regions for ch1
35 * and ch2 overlap, and host cannot get access to them at the
36 * same time. Hide the ch2 from U-Boot.
37 */
38 },
39 {
40 .soc_id = UNIPHIER_LD4_ID,
41 .sparse_ch1_base = 0xc0000000,
42 },
43 {
44 .soc_id = UNIPHIER_PRO4_ID,
45 .sparse_ch1_base = 0xa0000000,
46 },
47 {
48 .soc_id = UNIPHIER_SLD8_ID,
49 .sparse_ch1_base = 0xc0000000,
50 },
51 {
52 .soc_id = UNIPHIER_PRO5_ID,
53 .sparse_ch1_base = 0xc0000000,
54 },
55 {
56 .soc_id = UNIPHIER_PXS2_ID,
57 .sparse_ch1_base = 0xc0000000,
58 .have_ch2 = 1,
59 },
60 {
61 .soc_id = UNIPHIER_LD6B_ID,
62 .sparse_ch1_base = 0xc0000000,
63 .have_ch2 = 1,
64 },
65 {
66 .soc_id = UNIPHIER_LD11_ID,
67 .sparse_ch1_base = 0xc0000000,
68 },
69 {
70 .soc_id = UNIPHIER_LD20_ID,
71 .sparse_ch1_base = 0xc0000000,
72 .have_ch2 = 1,
73 },
74 {
75 .soc_id = UNIPHIER_PXS3_ID,
76 .sparse_ch1_base = 0xc0000000,
77 .have_ch2 = 1,
78 },
79};
80UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
81
Masahiro Yamada3dc80972017-02-05 10:52:12 +090082struct uniphier_dram_map {
83 unsigned long base;
84 unsigned long size;
85};
86
87static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
Masahiro Yamadab4782cd2015-09-11 20:17:49 +090088{
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +090089 const struct uniphier_memif_data *data;
90 unsigned long size;
91 u32 val;
Masahiro Yamadab4782cd2015-09-11 20:17:49 +090092
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +090093 data = uniphier_get_memif_data();
94 if (!data) {
95 pr_err("unsupported SoC\n");
96 return -EINVAL;
97 }
Masahiro Yamadab4782cd2015-09-11 20:17:49 +090098
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +090099 val = readl(SG_MEMCONF);
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900100
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900101 /* set up ch0 */
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900102 dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900103
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900104 switch (val & SG_MEMCONF_CH0_SZ_MASK) {
105 case SG_MEMCONF_CH0_SZ_64M:
106 size = SZ_64M;
107 break;
108 case SG_MEMCONF_CH0_SZ_128M:
109 size = SZ_128M;
110 break;
111 case SG_MEMCONF_CH0_SZ_256M:
112 size = SZ_256M;
113 break;
114 case SG_MEMCONF_CH0_SZ_512M:
115 size = SZ_512M;
116 break;
117 case SG_MEMCONF_CH0_SZ_1G:
118 size = SZ_1G;
119 break;
120 default:
Masahiro Yamada1566db92017-02-20 12:09:00 +0900121 pr_err("error: invalid value is set to MEMCONF ch0 size\n");
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900122 return -EINVAL;
Masahiro Yamadaa90b1102016-03-29 20:18:45 +0900123 }
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900124
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900125 if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
126 size *= 2;
127
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900128 dram_map[0].size = size;
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900129
130 /* set up ch1 */
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900131 dram_map[1].base = dram_map[0].base + size;
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900132
133 if (val & SG_MEMCONF_SPARSEMEM) {
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900134 if (dram_map[1].base > data->sparse_ch1_base) {
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900135 pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
136 pr_warn("Only ch0 is available\n");
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900137 dram_map[1].base = 0;
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900138 return 0;
139 }
140
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900141 dram_map[1].base = data->sparse_ch1_base;
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900142 }
143
144 switch (val & SG_MEMCONF_CH1_SZ_MASK) {
145 case SG_MEMCONF_CH1_SZ_64M:
146 size = SZ_64M;
147 break;
148 case SG_MEMCONF_CH1_SZ_128M:
149 size = SZ_128M;
150 break;
151 case SG_MEMCONF_CH1_SZ_256M:
152 size = SZ_256M;
153 break;
154 case SG_MEMCONF_CH1_SZ_512M:
155 size = SZ_512M;
156 break;
157 case SG_MEMCONF_CH1_SZ_1G:
158 size = SZ_1G;
159 break;
160 default:
Masahiro Yamada1566db92017-02-20 12:09:00 +0900161 pr_err("error: invalid value is set to MEMCONF ch1 size\n");
Masahiro Yamadaa90b1102016-03-29 20:18:45 +0900162 return -EINVAL;
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900163 }
Masahiro Yamadaa90b1102016-03-29 20:18:45 +0900164
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900165 if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
166 size *= 2;
Masahiro Yamadaa90b1102016-03-29 20:18:45 +0900167
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900168 dram_map[1].size = size;
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900169
Masahiro Yamada95beeed2017-02-20 12:10:05 +0900170 if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900171 return 0;
172
173 /* set up ch2 */
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900174 dram_map[2].base = dram_map[1].base + size;
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900175
176 switch (val & SG_MEMCONF_CH2_SZ_MASK) {
177 case SG_MEMCONF_CH2_SZ_64M:
178 size = SZ_64M;
179 break;
180 case SG_MEMCONF_CH2_SZ_128M:
181 size = SZ_128M;
182 break;
183 case SG_MEMCONF_CH2_SZ_256M:
184 size = SZ_256M;
185 break;
186 case SG_MEMCONF_CH2_SZ_512M:
187 size = SZ_512M;
188 break;
189 case SG_MEMCONF_CH2_SZ_1G:
190 size = SZ_1G;
191 break;
192 default:
Masahiro Yamada1566db92017-02-20 12:09:00 +0900193 pr_err("error: invalid value is set to MEMCONF ch2 size\n");
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900194 return -EINVAL;
195 }
196
197 if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
198 size *= 2;
199
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900200 dram_map[2].size = size;
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900201
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900202 return 0;
203}
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900204
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900205int dram_init(void)
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900206{
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900207 struct uniphier_dram_map dram_map[3] = {};
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900208 int ret, i;
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900209
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900210 gd->ram_size = 0;
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900211
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900212 ret = uniphier_memconf_decode(dram_map);
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900213 if (ret)
214 return ret;
215
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900216 for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900217
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900218 if (!dram_map[i].size)
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900219 break;
220
221 /*
222 * U-Boot relocates itself to the tail of the memory region,
223 * but it does not expect sparse memory. We use the first
224 * contiguous chunk here.
225 */
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900226 if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
227 dram_map[i].base)
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900228 break;
229
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900230 gd->ram_size += dram_map[i].size;
Masahiro Yamadaa90b1102016-03-29 20:18:45 +0900231 }
232
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900233 return 0;
234}
Masahiro Yamadaa90b1102016-03-29 20:18:45 +0900235
Simon Glass2f949c32017-03-31 08:40:32 -0600236int dram_init_banksize(void)
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900237{
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900238 struct uniphier_dram_map dram_map[3] = {};
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900239 int i;
240
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900241 uniphier_memconf_decode(dram_map);
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900242
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900243 for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
Masahiro Yamadad97c1cb2017-01-28 06:53:43 +0900244 if (i >= ARRAY_SIZE(gd->bd->bi_dram))
245 break;
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900246
Masahiro Yamada3dc80972017-02-05 10:52:12 +0900247 gd->bd->bi_dram[i].start = dram_map[i].base;
248 gd->bd->bi_dram[i].size = dram_map[i].size;
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900249 }
Simon Glass2f949c32017-03-31 08:40:32 -0600250
251 return 0;
Masahiro Yamada460483c2016-06-17 19:24:29 +0900252}
253
254#ifdef CONFIG_OF_BOARD_SETUP
255/*
256 * The DRAM PHY requires 64 byte scratch area in each DRAM channel
257 * for its dynamic PHY training feature.
258 */
259int ft_board_setup(void *fdt, bd_t *bd)
260{
Masahiro Yamada460483c2016-06-17 19:24:29 +0900261 unsigned long rsv_addr;
262 const unsigned long rsv_size = 64;
Masahiro Yamada0197f632017-01-28 06:53:44 +0900263 int i, ret;
Masahiro Yamada460483c2016-06-17 19:24:29 +0900264
Masahiro Yamada31649052017-01-21 18:05:26 +0900265 if (uniphier_get_soc_id() != UNIPHIER_LD20_ID)
Masahiro Yamada460483c2016-06-17 19:24:29 +0900266 return 0;
267
Masahiro Yamada0197f632017-01-28 06:53:44 +0900268 for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
Masahiro Yamadab14071d2017-02-20 17:13:32 +0900269 if (!gd->bd->bi_dram[i].size)
270 continue;
271
Masahiro Yamada0197f632017-01-28 06:53:44 +0900272 rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size;
Masahiro Yamada460483c2016-06-17 19:24:29 +0900273 rsv_addr -= rsv_size;
274
275 ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
276 if (ret)
277 return -ENOSPC;
278
279 printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",
280 rsv_addr, rsv_size);
281 }
282
283 return 0;
Masahiro Yamadab4782cd2015-09-11 20:17:49 +0900284}
Masahiro Yamada460483c2016-06-17 19:24:29 +0900285#endif