| Marek Vasut | 62df312 | 2017-05-13 15:57:39 +0200 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/include/asm/arch-rcar_gen3/r8a7796.h |
| 3 | * This file defines registers and value for r8a7796. |
| 4 | * |
| 5 | * Copyright (C) 2016 Renesas Electronics Corporation |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef __ASM_ARCH_R8A7796_H |
| 11 | #define __ASM_ARCH_R8A7796_H |
| 12 | |
| 13 | #include "rcar-gen3-base.h" |
| 14 | |
| 15 | /* Module stop control/status register bits */ |
| 16 | #define MSTP0_BITS 0x00200000 |
| 17 | #define MSTP1_BITS 0xFFFFFFFF |
| 18 | #define MSTP2_BITS 0x340E2FDC |
| 19 | #define MSTP3_BITS 0xFFFFFFDF |
| 20 | #define MSTP4_BITS 0x80000184 |
| 21 | #define MSTP5_BITS 0xC3FFFFFF |
| 22 | #define MSTP6_BITS 0xFFFFFFFF |
| 23 | #define MSTP7_BITS 0xFFFFFFFF |
| 24 | #define MSTP8_BITS 0x01F1FFF7 |
| 25 | #define MSTP9_BITS 0xFFFFFFFE |
| 26 | #define MSTP10_BITS 0xFFFEFFE0 |
| 27 | #define MSTP11_BITS 0x000000B7 |
| 28 | |
| 29 | /* SDHI */ |
| 30 | #define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 |
| 31 | #define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 |
| 32 | #define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ |
| 33 | #define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ |
| 34 | #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 |
| 35 | |
| Marek Vasut | 62df312 | 2017-05-13 15:57:39 +0200 | [diff] [blame] | 36 | #endif /* __ASM_ARCH_R8A7796_H */ |