| Andy Yan | b9909aa | 2017-05-15 17:49:56 +0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2017 Rockchip Electronics Co., Ltd |
| 3 | * Author: Andy Yan <andy.yan@rock-chips.com> |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | #ifndef _ASM_ARCH_CRU_RK3368_H |
| 7 | #define _ASM_ARCH_CRU_RK3368_H |
| 8 | |
| 9 | #include <common.h> |
| 10 | |
| 11 | |
| 12 | /* RK3368 clock numbers */ |
| 13 | enum rk3368_pll_id { |
| 14 | APLLB, |
| 15 | APLLL, |
| 16 | DPLL, |
| 17 | CPLL, |
| 18 | GPLL, |
| 19 | NPLL, |
| 20 | PLL_COUNT, |
| 21 | }; |
| 22 | |
| 23 | struct rk3368_cru { |
| 24 | struct rk3368_pll { |
| 25 | unsigned int con0; |
| 26 | unsigned int con1; |
| 27 | unsigned int con2; |
| 28 | unsigned int con3; |
| 29 | } pll[6]; |
| 30 | unsigned int reserved[0x28]; |
| 31 | unsigned int clksel_con[56]; |
| 32 | unsigned int reserved1[8]; |
| 33 | unsigned int clkgate_con[25]; |
| 34 | unsigned int reserved2[7]; |
| 35 | unsigned int glb_srst_fst_val; |
| 36 | unsigned int glb_srst_snd_val; |
| 37 | unsigned int reserved3[0x1e]; |
| 38 | unsigned int softrst_con[15]; |
| 39 | unsigned int reserved4[0x11]; |
| 40 | unsigned int misc_con; |
| 41 | unsigned int glb_cnt_th; |
| 42 | unsigned int glb_rst_con; |
| 43 | unsigned int glb_rst_st; |
| 44 | unsigned int reserved5[0x1c]; |
| 45 | unsigned int sdmmc_con[2]; |
| 46 | unsigned int sdio0_con[2]; |
| 47 | unsigned int sdio1_con[2]; |
| 48 | unsigned int emmc_con[2]; |
| 49 | }; |
| 50 | check_member(rk3368_cru, emmc_con[1], 0x41c); |
| 51 | |
| 52 | struct rk3368_clk_priv { |
| 53 | struct rk3368_cru *cru; |
| 54 | ulong rate; |
| 55 | bool has_bwadj; |
| 56 | }; |
| 57 | |
| 58 | enum { |
| 59 | /* PLL CON0 */ |
| 60 | PLL_NR_SHIFT = 8, |
| 61 | PLL_NR_MASK = GENMASK(13, 8), |
| 62 | PLL_OD_SHIFT = 0, |
| 63 | PLL_OD_MASK = GENMASK(3, 0), |
| 64 | |
| 65 | /* PLL CON1 */ |
| 66 | PLL_LOCK_STA = BIT(31), |
| 67 | PLL_NF_SHIFT = 0, |
| 68 | PLL_NF_MASK = GENMASK(12, 0), |
| 69 | |
| 70 | /* PLL CON2 */ |
| 71 | PLL_BWADJ_SHIFT = 0, |
| 72 | PLL_BWADJ_MASK = GENMASK(11, 0), |
| 73 | |
| 74 | /* PLL CON3 */ |
| 75 | PLL_MODE_SHIFT = 8, |
| 76 | PLL_MODE_MASK = GENMASK(9, 8), |
| 77 | PLL_MODE_SLOW = 0, |
| 78 | PLL_MODE_NORMAL = 1, |
| 79 | PLL_MODE_DEEP_SLOW = 3, |
| 80 | PLL_RESET_SHIFT = 5, |
| 81 | PLL_RESET = 1, |
| 82 | PLL_RESET_MASK = GENMASK(5, 5), |
| 83 | |
| 84 | /* CLKSEL12_CON */ |
| 85 | MCU_STCLK_DIV_SHIFT = 8, |
| 86 | MCU_STCLK_DIV_MASK = GENMASK(10, 8), |
| 87 | MCU_PLL_SEL_SHIFT = 7, |
| 88 | MCU_PLL_SEL_MASK = BIT(7), |
| 89 | MCU_PLL_SEL_CPLL = 0, |
| 90 | MCU_PLL_SEL_GPLL = 1, |
| 91 | MCU_CLK_DIV_SHIFT = 0, |
| 92 | MCU_CLK_DIV_MASK = GENMASK(4, 0), |
| 93 | |
| 94 | /* CLKSEL51_CON */ |
| 95 | MMC_PLL_SEL_SHIFT = 8, |
| 96 | MMC_PLL_SEL_MASK = GENMASK(9, 8), |
| 97 | MMC_PLL_SEL_CPLL = 0, |
| 98 | MMC_PLL_SEL_GPLL, |
| 99 | MMC_PLL_SEL_USBPHY_480M, |
| 100 | MMC_PLL_SEL_24M, |
| 101 | MMC_CLK_DIV_SHIFT = 0, |
| 102 | MMC_CLK_DIV_MASK = GENMASK(6, 0), |
| 103 | |
| 104 | /* SOFTRST1_CON */ |
| 105 | MCU_PO_SRST_MASK = BIT(13), |
| 106 | MCU_SYS_SRST_MASK = BIT(12), |
| 107 | |
| 108 | /* GLB_RST_CON */ |
| 109 | PMU_GLB_SRST_CTRL_SHIFT = 2, |
| 110 | PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), |
| 111 | PMU_RST_BY_FST_GLB_SRST = 0, |
| 112 | PMU_RST_BY_SND_GLB_SRST = 1, |
| 113 | PMU_RST_DISABLE = 2, |
| 114 | WDT_GLB_SRST_CTRL_SHIFT = 1, |
| 115 | WDT_GLB_SRST_CTRL_MASK = BIT(1), |
| 116 | WDT_TRIGGER_SND_GLB_SRST = 0, |
| 117 | WDT_TRIGGER_FST_GLB_SRST = 1, |
| 118 | TSADC_GLB_SRST_CTRL_SHIFT = 0, |
| 119 | TSADC_GLB_SRST_CTRL_MASK = BIT(0), |
| 120 | TSADC_TRIGGER_SND_GLB_SRST = 0, |
| 121 | TSADC_TRIGGER_FST_GLB_SRST = 1, |
| 122 | |
| 123 | }; |
| 124 | #endif |