Graeme Russ | 85cc39f | 2009-02-24 21:14:32 +1100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* stuff specific for the sc520, but independent of implementation */ |
| 25 | |
| 26 | #include <common.h> |
| 27 | #include <pci.h> |
| 28 | #include <asm/pci.h> |
| 29 | #include <asm/ic/sc520.h> |
| 30 | |
| 31 | static struct { |
| 32 | u8 priority; |
| 33 | u16 level_reg; |
| 34 | u8 level_bit; |
| 35 | } sc520_irq[] = { |
| 36 | { SC520_IRQ0, SC520_MPICMODE, 0x01 }, |
| 37 | { SC520_IRQ1, SC520_MPICMODE, 0x02 }, |
| 38 | { SC520_IRQ2, SC520_SL1PICMODE, 0x02 }, |
| 39 | { SC520_IRQ3, SC520_MPICMODE, 0x08 }, |
| 40 | { SC520_IRQ4, SC520_MPICMODE, 0x10 }, |
| 41 | { SC520_IRQ5, SC520_MPICMODE, 0x20 }, |
| 42 | { SC520_IRQ6, SC520_MPICMODE, 0x40 }, |
| 43 | { SC520_IRQ7, SC520_MPICMODE, 0x80 }, |
| 44 | |
| 45 | { SC520_IRQ8, SC520_SL1PICMODE, 0x01 }, |
| 46 | { SC520_IRQ9, SC520_SL1PICMODE, 0x02 }, |
| 47 | { SC520_IRQ10, SC520_SL1PICMODE, 0x04 }, |
| 48 | { SC520_IRQ11, SC520_SL1PICMODE, 0x08 }, |
| 49 | { SC520_IRQ12, SC520_SL1PICMODE, 0x10 }, |
| 50 | { SC520_IRQ13, SC520_SL1PICMODE, 0x20 }, |
| 51 | { SC520_IRQ14, SC520_SL1PICMODE, 0x40 }, |
| 52 | { SC520_IRQ15, SC520_SL1PICMODE, 0x80 } |
| 53 | }; |
| 54 | |
| 55 | |
| 56 | /* The interrupt used for PCI INTA-INTD */ |
| 57 | int sc520_pci_ints[15] = { |
| 58 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 59 | -1, -1, -1, -1, -1, -1, -1 |
| 60 | }; |
| 61 | |
| 62 | /* utility function to configure a pci interrupt */ |
| 63 | int pci_sc520_set_irq(int pci_pin, int irq) |
| 64 | { |
| 65 | int i; |
| 66 | |
| 67 | # if 1 |
| 68 | printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); |
| 69 | #endif |
| 70 | if (irq < 0 || irq > 15) { |
| 71 | return -1; /* illegal irq */ |
| 72 | } |
| 73 | |
| 74 | if (pci_pin < 0 || pci_pin > 15) { |
| 75 | return -1; /* illegal pci int pin */ |
| 76 | } |
| 77 | |
| 78 | /* first disable any non-pci interrupt source that use |
| 79 | * this level */ |
| 80 | for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) { |
| 81 | if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) { |
| 82 | continue; |
| 83 | } |
| 84 | if (read_mmcr_byte(i) == sc520_irq[irq].priority) { |
| 85 | write_mmcr_byte(i, SC520_IRQ_DISABLED); |
| 86 | } |
| 87 | } |
| 88 | |
| 89 | /* Set the trigger to level */ |
| 90 | write_mmcr_byte(sc520_irq[irq].level_reg, |
| 91 | read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit); |
| 92 | |
| 93 | |
| 94 | if (pci_pin < 4) { |
| 95 | /* PCI INTA-INTD */ |
| 96 | /* route the interrupt */ |
| 97 | write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority); |
| 98 | |
| 99 | |
| 100 | } else { |
| 101 | /* GPIRQ0-GPIRQ10 used for additional PCI INTS */ |
| 102 | write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority); |
| 103 | |
| 104 | /* also set the polarity in this case */ |
| 105 | write_mmcr_word(SC520_INTPINPOL, |
| 106 | read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4))); |
| 107 | |
| 108 | } |
| 109 | |
| 110 | /* register the pin */ |
| 111 | sc520_pci_ints[pci_pin] = irq; |
| 112 | |
| 113 | |
| 114 | return 0; /* OK */ |
| 115 | } |
| 116 | |
| 117 | void pci_sc520_init(struct pci_controller *hose) |
| 118 | { |
| 119 | hose->first_busno = 0; |
| 120 | hose->last_busno = 0xff; |
| 121 | |
| 122 | /* System memory space */ |
| 123 | pci_set_region(hose->regions + 0, |
| 124 | SC520_PCI_MEMORY_BUS, |
| 125 | SC520_PCI_MEMORY_PHYS, |
| 126 | SC520_PCI_MEMORY_SIZE, |
| 127 | PCI_REGION_MEM | PCI_REGION_MEMORY); |
| 128 | |
| 129 | /* PCI memory space */ |
| 130 | pci_set_region(hose->regions + 1, |
| 131 | SC520_PCI_MEM_BUS, |
| 132 | SC520_PCI_MEM_PHYS, |
| 133 | SC520_PCI_MEM_SIZE, |
| 134 | PCI_REGION_MEM); |
| 135 | |
| 136 | /* ISA/PCI memory space */ |
| 137 | pci_set_region(hose->regions + 2, |
| 138 | SC520_ISA_MEM_BUS, |
| 139 | SC520_ISA_MEM_PHYS, |
| 140 | SC520_ISA_MEM_SIZE, |
| 141 | PCI_REGION_MEM); |
| 142 | |
| 143 | /* PCI I/O space */ |
| 144 | pci_set_region(hose->regions + 3, |
| 145 | SC520_PCI_IO_BUS, |
| 146 | SC520_PCI_IO_PHYS, |
| 147 | SC520_PCI_IO_SIZE, |
| 148 | PCI_REGION_IO); |
| 149 | |
| 150 | /* ISA/PCI I/O space */ |
| 151 | pci_set_region(hose->regions + 4, |
| 152 | SC520_ISA_IO_BUS, |
| 153 | SC520_ISA_IO_PHYS, |
| 154 | SC520_ISA_IO_SIZE, |
| 155 | PCI_REGION_IO); |
| 156 | |
| 157 | hose->region_count = 5; |
| 158 | |
| 159 | pci_setup_type1(hose, |
| 160 | SC520_REG_ADDR, |
| 161 | SC520_REG_DATA); |
| 162 | |
| 163 | pci_register_hose(hose); |
| 164 | |
| 165 | hose->last_busno = pci_hose_scan(hose); |
| 166 | |
| 167 | /* enable target memory acceses on host brige */ |
| 168 | pci_write_config_word(0, PCI_COMMAND, |
| 169 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 170 | |
| 171 | } |