| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2015 Xilinx, Inc, |
| 4 | * Michal Simek <michal.simek@xilinx.com> |
| Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ZYNQMPPL_H_ |
| 8 | #define _ZYNQMPPL_H_ |
| 9 | |
| 10 | #include <xilinx.h> |
| 11 | |
| Michal Simek | 8111aff | 2016-02-01 15:05:58 +0100 | [diff] [blame] | 12 | #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 |
| Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 13 | #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 |
| Nitin Jain | d9361d4 | 2018-02-16 17:29:54 +0530 | [diff] [blame] | 14 | #define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017 |
| Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 15 | #define ZYNQMP_FPGA_OP_INIT (1 << 0) |
| 16 | #define ZYNQMP_FPGA_OP_LOAD (1 << 1) |
| 17 | #define ZYNQMP_FPGA_OP_DONE (1 << 2) |
| 18 | |
| Soren Brinkmann | d7696a5 | 2016-09-29 11:44:41 -0700 | [diff] [blame] | 19 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 |
| 20 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ |
| 21 | ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) |
| 22 | #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 |
| Michal Simek | f97de33 | 2017-06-28 15:40:32 +0200 | [diff] [blame] | 23 | #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT) |
| Soren Brinkmann | d7696a5 | 2016-09-29 11:44:41 -0700 | [diff] [blame] | 24 | |
| Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 25 | extern struct xilinx_fpga_op zynqmp_op; |
| 26 | |
| 27 | #define XILINX_ZYNQMP_DESC \ |
| 28 | { xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op } |
| 29 | |
| 30 | #endif /* _ZYNQMPPL_H_ */ |