Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 6e773f91bd59cd2bb8769ecd89ac3435719bfdc9 / . / configs / tinker-rk3288_defconfig
blob: 93286084525dad92c6d7248d6ae50a1e704ba25a [file] [log] [blame]
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Kever Yang614f2532019-07-01 11:49:13 +0800[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x01000000
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]4CONFIG_SPL_GPIO_SUPPORT=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]5CONFIG_ROCKCHIP_RK3288=y
Eddie Cai1e1a79f2017-01-18 11:03:54 +0800[diff] [blame]6CONFIG_TARGET_TINKER_RK3288=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
Kever Yang614f2532019-07-01 11:49:13 +0800[diff] [blame]8CONFIG_SPL_SIZE_LIMIT=307200
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]9CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]10CONFIG_DEBUG_UART_BASE=0xff690000
11CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]12CONFIG_DEBUG_UART=y
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]13# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]14CONFIG_USE_PREBOOT=y
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]15CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]16CONFIG_CONSOLE_MUX=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]17CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb"
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]18# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]19CONFIG_DISPLAY_BOARDINFO_LATE=y
Jagan Teki8aa6c992019-09-17 11:40:41 +0530[diff] [blame]20CONFIG_SPL_STACK_R=y
21CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]22CONFIG_SPL_I2C_SUPPORT=y
23CONFIG_SPL_POWER_SUPPORT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]24CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]25CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]26CONFIG_CMD_I2C=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]27CONFIG_CMD_MMC=y
28CONFIG_CMD_SF=y
29CONFIG_CMD_SPI=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]30CONFIG_CMD_USB=y
Urja Rannikko17dd9d32019-05-13 13:51:04 +0000[diff] [blame]31CONFIG_CMD_USB_MASS_STORAGE=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]32# CONFIG_CMD_SETEXPR is not set
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]33CONFIG_CMD_CACHE=y
34CONFIG_CMD_TIME=y
35CONFIG_CMD_PMIC=y
36CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]37# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]38# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]39CONFIG_SPL_PARTITION_UUIDS=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]40CONFIG_SPL_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]41CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
Kever Yang614f2532019-07-01 11:49:13 +0800[diff] [blame]42CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]43CONFIG_ENV_IS_IN_MMC=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]44CONFIG_REGMAP=y
45CONFIG_SPL_REGMAP=y
46CONFIG_SYSCON=y
47CONFIG_SPL_SYSCON=y
48# CONFIG_SPL_SIMPLE_BUS is not set
49CONFIG_CLK=y
50CONFIG_SPL_CLK=y
Alex Kiernane80d2942018-05-29 15:30:55 +0000[diff] [blame]51CONFIG_FASTBOOT_FLASH=y
52CONFIG_FASTBOOT_FLASH_MMC_DEV=0
53CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]54CONFIG_ROCKCHIP_GPIO=y
55CONFIG_SYS_I2C_ROCKCHIP=y
Jonas Karlman269a37f2017-04-22 08:57:54 +0000[diff] [blame]56CONFIG_MISC=y
57CONFIG_I2C_EEPROM=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]58CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]59CONFIG_MMC_DW_ROCKCHIP=y
Vignesh Re57ea112019-02-05 11:29:10 +0530[diff] [blame]60CONFIG_SPI_FLASH=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]61CONFIG_SF_DEFAULT_SPEED=20000000
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]62CONFIG_DM_ETH=y
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]63CONFIG_ETH_DESIGNWARE=y
64CONFIG_GMAC_ROCKCHIP=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]65CONFIG_PINCTRL=y
66CONFIG_SPL_PINCTRL=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]67CONFIG_DM_PMIC=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]68CONFIG_PMIC_RK8XX=y
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]69CONFIG_SPL_DM_REGULATOR=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]70CONFIG_DM_REGULATOR_FIXED=y
Michael Trimarchi5e2d2382019-09-17 11:40:42 +0530[diff] [blame]71CONFIG_SPL_DM_REGULATOR_FIXED=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]72CONFIG_REGULATOR_RK8XX=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]73CONFIG_PWM_ROCKCHIP=y
74CONFIG_RAM=y
75CONFIG_SPL_RAM=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]76CONFIG_DEBUG_UART_SHIFT=2
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]77CONFIG_SYSRESET=y
Eddie Caid1ba93e2017-03-07 12:47:07 +0800[diff] [blame]78CONFIG_USB=y
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]79CONFIG_USB_DWC2=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]80CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]81CONFIG_USB_GADGET=y
Maxime Ripard7f78b9d2017-09-07 08:58:08 +0200[diff] [blame]82CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
83CONFIG_USB_GADGET_VENDOR_NUM=0x2207
84CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]85CONFIG_USB_GADGET_DWC2_OTG=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]86CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]87CONFIG_USB_ETHER_ASIX=y
88CONFIG_USB_ETHER_SMSC95XX=y
Xu Ziyuan535b3dc2016-08-01 08:46:19 +0800[diff] [blame]89CONFIG_CMD_DHRYSTONE=y
90CONFIG_ERRNO_STR=y