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git01.mediatek.com / filogic / uboot / 6e5c0191c04df1913982bc1a335863db82936578 / . / drivers / reset / ast2500-reset.c
blob: b2c89e1f1e2992f4261cfc5f7a6203e34374351a [file] [log] [blame]
maxims@google.com750875c2017-04-17 12:00:24 -0700[diff] [blame]1/*
2 * Copyright 2017 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <misc.h>
10#include <reset.h>
11#include <reset-uclass.h>
12#include <wdt.h>
13#include <asm/io.h>
14#include <asm/arch/scu_ast2500.h>
15#include <asm/arch/wdt.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19struct ast2500_reset_priv {
20 /* WDT used to perform resets. */
21 struct udevice *wdt;
22 struct ast2500_scu *scu;
23};
24
25static int ast2500_ofdata_to_platdata(struct udevice *dev)
26{
27 struct ast2500_reset_priv *priv = dev_get_priv(dev);
28 int ret;
29
30 ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
31 &priv->wdt);
32 if (ret) {
33 debug("%s: can't find WDT for reset controller", __func__);
34 return ret;
35 }
36
37 return 0;
38}
39
40static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
41{
42 struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
43 u32 reset_mode, reset_mask;
44 bool reset_sdram;
45 int ret;
46
47 /*
48 * To reset SDRAM, a specifal flag in SYSRESET register
49 * needs to be enabled first
50 */
51 reset_mode = ast_reset_mode_from_flags(reset_ctl->id);
52 reset_mask = ast_reset_mask_from_flags(reset_ctl->id);
53 reset_sdram = reset_mode == WDT_CTRL_RESET_SOC &&
54 (reset_mask & WDT_RESET_SDRAM);
55
56 if (reset_sdram) {
57 ast_scu_unlock(priv->scu);
58 setbits_le32(&priv->scu->sysreset_ctrl1,
59 SCU_SYSRESET_SDRAM_WDT);
60 ret = wdt_expire_now(priv->wdt, reset_ctl->id);
61 clrbits_le32(&priv->scu->sysreset_ctrl1,
62 SCU_SYSRESET_SDRAM_WDT);
63 ast_scu_lock(priv->scu);
64 } else {
65 ret = wdt_expire_now(priv->wdt, reset_ctl->id);
66 }
67
68 return ret;
69}
70
71static int ast2500_reset_request(struct reset_ctl *reset_ctl)
72{
73 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
74 reset_ctl->dev, reset_ctl->id);
75
76 return 0;
77}
78
79static int ast2500_reset_probe(struct udevice *dev)
80{
81 struct ast2500_reset_priv *priv = dev_get_priv(dev);
82
83 priv->scu = ast_get_scu();
84
85 return 0;
86}
87
88static const struct udevice_id ast2500_reset_ids[] = {
89 { .compatible = "aspeed,ast2500-reset" },
90 { }
91};
92
93struct reset_ops ast2500_reset_ops = {
94 .rst_assert = ast2500_reset_assert,
95 .request = ast2500_reset_request,
96};
97
98U_BOOT_DRIVER(ast2500_reset) = {
99 .name = "ast2500_reset",
100 .id = UCLASS_RESET,
101 .of_match = ast2500_reset_ids,
102 .probe = ast2500_reset_probe,
103 .ops = &ast2500_reset_ops,
104 .ofdata_to_platdata = ast2500_ofdata_to_platdata,
105 .priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
106};