blob: 6ac4f83bd1cf34c38cae3aa8a1d6f19fbc567e8f [file] [log] [blame]
Kuo-Jung Sud123ab82013-05-06 20:32:51 +00001/*
2 * Faraday MMC/SD Host Controller
3 *
4 * (C) Copyright 2010 Faraday Technology
5 * Dante Su <dantesu@faraday-tech.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Kuo-Jung Sud123ab82013-05-06 20:32:51 +00008 */
9
10#include <common.h>
11#include <malloc.h>
12#include <part.h>
13#include <mmc.h>
14
Rick Chenf7a4adb2017-08-28 16:44:11 +080015#include <linux/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090016#include <linux/errno.h>
Kuo-Jung Sud123ab82013-05-06 20:32:51 +000017#include <asm/byteorder.h>
18#include <faraday/ftsdc010.h>
Rick Chenf7a4adb2017-08-28 16:44:11 +080019#include "ftsdc010_mci.h"
Kuo-Jung Sud123ab82013-05-06 20:32:51 +000020
21#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
22#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
23
Kuo-Jung Sud123ab82013-05-06 20:32:51 +000024static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
25{
26 struct ftsdc010_chip *chip = mmc->priv;
27 struct ftsdc010_mmc __iomem *regs = chip->regs;
Jaehoon Chung7825d202016-07-19 16:33:36 +090028 int ret = -ETIMEDOUT;
Kuo-Jung Sud123ab82013-05-06 20:32:51 +000029 uint32_t ts, st;
30 uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
31 uint32_t arg = mmc_cmd->cmdarg;
32 uint32_t flags = mmc_cmd->resp_type;
33
34 cmd |= FTSDC010_CMD_CMD_EN;
35
36 if (chip->acmd) {
37 cmd |= FTSDC010_CMD_APP_CMD;
38 chip->acmd = 0;
39 }
40
41 if (flags & MMC_RSP_PRESENT)
42 cmd |= FTSDC010_CMD_NEED_RSP;
43
44 if (flags & MMC_RSP_136)
45 cmd |= FTSDC010_CMD_LONG_RSP;
46
47 writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
48 &regs->clr);
49 writel(arg, &regs->argu);
50 writel(cmd, &regs->cmd);
51
52 if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
53 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
54 if (readl(&regs->status) & FTSDC010_STATUS_CMD_SEND) {
55 writel(FTSDC010_STATUS_CMD_SEND, &regs->clr);
56 ret = 0;
57 break;
58 }
59 }
60 } else {
61 st = 0;
62 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
63 st = readl(&regs->status);
64 writel(st & FTSDC010_STATUS_RSP_MASK, &regs->clr);
65 if (st & FTSDC010_STATUS_RSP_MASK)
66 break;
67 }
68 if (st & FTSDC010_STATUS_RSP_CRC_OK) {
69 if (flags & MMC_RSP_136) {
70 mmc_cmd->response[0] = readl(&regs->rsp3);
71 mmc_cmd->response[1] = readl(&regs->rsp2);
72 mmc_cmd->response[2] = readl(&regs->rsp1);
73 mmc_cmd->response[3] = readl(&regs->rsp0);
74 } else {
75 mmc_cmd->response[0] = readl(&regs->rsp0);
76 }
77 ret = 0;
78 } else {
79 debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
80 mmc_cmd->cmdidx, st);
81 }
82 }
83
84 if (ret) {
85 debug("ftsdc010: cmd timeout (op code=%d)\n",
86 mmc_cmd->cmdidx);
87 } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
88 chip->acmd = 1;
89 }
90
91 return ret;
92}
93
94static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
95{
96 struct ftsdc010_chip *chip = mmc->priv;
97 struct ftsdc010_mmc __iomem *regs = chip->regs;
98 uint32_t div;
99
100 for (div = 0; div < 0x7f; ++div) {
101 if (rate >= chip->sclk / (2 * (div + 1)))
102 break;
103 }
104 chip->rate = chip->sclk / (2 * (div + 1));
105
106 writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr);
107
108 if (IS_SD(mmc)) {
109 setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD);
110
111 if (chip->rate > 25000000)
112 setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
113 else
114 clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
115 }
116}
117
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000118static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
119{
Jaehoon Chung7825d202016-07-19 16:33:36 +0900120 int ret = -ETIMEDOUT;
Rick Chenf7a4adb2017-08-28 16:44:11 +0800121 uint32_t st, timeout = 10000000;
122 while (timeout--) {
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000123 st = readl(&regs->status);
124 if (!(st & mask))
125 continue;
126 writel(st & mask, &regs->clr);
127 ret = 0;
128 break;
129 }
130
Rick Chen22223f02017-08-25 14:02:13 +0800131 if (ret){
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000132 debug("ftsdc010: wait st(0x%x) timeout\n", mask);
Rick Chen22223f02017-08-25 14:02:13 +0800133 }
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000134
135 return ret;
136}
137
138/*
139 * u-boot mmc api
140 */
Rick Chenf7a4adb2017-08-28 16:44:11 +0800141#ifdef CONFIG_DM_MMC
142static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
143 struct mmc_data *data)
144{
145 struct mmc *mmc = mmc_get_mmc_dev(dev);
146#else
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000147static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
148 struct mmc_data *data)
149{
Rick Chenf7a4adb2017-08-28 16:44:11 +0800150#endif
Jaehoon Chung7825d202016-07-19 16:33:36 +0900151 int ret = -EOPNOTSUPP;
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000152 uint32_t len = 0;
153 struct ftsdc010_chip *chip = mmc->priv;
154 struct ftsdc010_mmc __iomem *regs = chip->regs;
155
156 if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
157 printf("ftsdc010: the card is write protected!\n");
158 return ret;
159 }
160
161 if (data) {
162 uint32_t dcr;
163
164 len = data->blocksize * data->blocks;
165
166 /* 1. data disable + fifo reset */
Gabor Juhos67a38f12013-05-26 12:11:27 +0200167 dcr = 0;
168#ifdef CONFIG_FTSDC010_SDIO
169 dcr |= FTSDC010_DCR_FIFO_RST;
170#endif
171 writel(dcr, &regs->dcr);
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000172
173 /* 2. clear status register */
174 writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
175 | FTSDC010_STATUS_FIFO_ORUN, &regs->clr);
176
177 /* 3. data timeout (1 sec) */
178 writel(chip->rate, &regs->dtr);
179
180 /* 4. data length (bytes) */
181 writel(len, &regs->dlr);
182
183 /* 5. data enable */
184 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
185 if (data->flags & MMC_DATA_WRITE)
186 dcr |= FTSDC010_DCR_DATA_WRITE;
187 writel(dcr, &regs->dcr);
188 }
189
190 ret = ftsdc010_send_cmd(mmc, cmd);
191 if (ret) {
192 printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
193 return ret;
194 }
195
196 if (!data)
197 return ret;
198
199 if (data->flags & MMC_DATA_WRITE) {
200 const uint8_t *buf = (const uint8_t *)data->src;
201
202 while (len > 0) {
203 int wlen;
204
205 /* wait for tx ready */
206 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
207 if (ret)
208 break;
209
210 /* write bytes to ftsdc010 */
211 for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
212 writel(*(uint32_t *)buf, &regs->dwr);
213 buf += 4;
214 wlen += 4;
215 }
216
217 len -= wlen;
218 }
219
220 } else {
221 uint8_t *buf = (uint8_t *)data->dest;
222
223 while (len > 0) {
224 int rlen;
225
226 /* wait for rx ready */
227 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
228 if (ret)
229 break;
230
231 /* fetch bytes from ftsdc010 */
232 for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
233 *(uint32_t *)buf = readl(&regs->dwr);
234 buf += 4;
235 rlen += 4;
236 }
237
238 len -= rlen;
239 }
240
241 }
242
243 if (!ret) {
244 ret = ftsdc010_wait(regs,
Rick Chen22223f02017-08-25 14:02:13 +0800245 FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000246 }
247
248 return ret;
249}
250
Rick Chenf7a4adb2017-08-28 16:44:11 +0800251#ifdef CONFIG_DM_MMC
252static int ftsdc010_set_ios(struct udevice *dev)
253{
254 struct mmc *mmc = mmc_get_mmc_dev(dev);
255#else
Jaehoon Chungb6cd1d32016-12-30 15:30:16 +0900256static int ftsdc010_set_ios(struct mmc *mmc)
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000257{
Rick Chenf7a4adb2017-08-28 16:44:11 +0800258#endif
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000259 struct ftsdc010_chip *chip = mmc->priv;
260 struct ftsdc010_mmc __iomem *regs = chip->regs;
261
262 ftsdc010_clkset(mmc, mmc->clock);
263
264 clrbits_le32(&regs->bwr, FTSDC010_BWR_MODE_MASK);
265 switch (mmc->bus_width) {
266 case 4:
267 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_4BIT);
268 break;
269 case 8:
270 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_8BIT);
271 break;
272 default:
273 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_1BIT);
274 break;
275 }
Jaehoon Chungb6cd1d32016-12-30 15:30:16 +0900276
277 return 0;
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000278}
279
Rick Chenf7a4adb2017-08-28 16:44:11 +0800280#ifdef CONFIG_DM_MMC
281static int ftsdc010_get_cd(struct udevice *dev)
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000282{
Rick Chenf7a4adb2017-08-28 16:44:11 +0800283 struct mmc *mmc = mmc_get_mmc_dev(dev);
284#else
285static int ftsdc010_get_cd(struct mmc *mmc)
286{
287#endif
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000288 struct ftsdc010_chip *chip = mmc->priv;
289 struct ftsdc010_mmc __iomem *regs = chip->regs;
Rick Chenf7a4adb2017-08-28 16:44:11 +0800290 return !(readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT);
291}
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000292
Rick Chenf7a4adb2017-08-28 16:44:11 +0800293#ifdef CONFIG_DM_MMC
294static int ftsdc010_get_wp(struct udevice *dev)
295{
296 struct mmc *mmc = mmc_get_mmc_dev(dev);
297#else
298static int ftsdc010_get_wp(struct mmc *mmc)
299{
300#endif
301 struct ftsdc010_chip *chip = mmc->priv;
302 struct ftsdc010_mmc __iomem *regs = chip->regs;
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000303 if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
304 printf("ftsdc010: write protected\n");
305 chip->wprot = 1;
306 }
307
Rick Chenf7a4adb2017-08-28 16:44:11 +0800308 return 0;
309}
310
311static int ftsdc010_init(struct mmc *mmc)
312{
313 struct ftsdc010_chip *chip = mmc->priv;
314 struct ftsdc010_mmc __iomem *regs = chip->regs;
315 uint32_t ts;
316
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000317 chip->fifo = (readl(&regs->feature) & 0xff) << 2;
318
319 /* 1. chip reset */
320 writel(FTSDC010_CMD_SDC_RST, &regs->cmd);
321 for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
322 if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST)
323 continue;
324 break;
325 }
326 if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST) {
327 printf("ftsdc010: reset failed\n");
Jaehoon Chung7825d202016-07-19 16:33:36 +0900328 return -EOPNOTSUPP;
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000329 }
330
331 /* 2. enter low speed mode (400k card detection) */
332 ftsdc010_clkset(mmc, 400000);
333
334 /* 3. interrupt disabled */
335 writel(0, &regs->int_mask);
336
337 return 0;
338}
339
Rick Chenf7a4adb2017-08-28 16:44:11 +0800340#ifdef CONFIG_DM_MMC
341int ftsdc010_probe(struct udevice *dev)
342{
343 struct mmc *mmc = mmc_get_mmc_dev(dev);
344 return ftsdc010_init(mmc);
345}
346
347const struct dm_mmc_ops dm_ftsdc010_ops = {
348 .send_cmd = ftsdc010_request,
349 .set_ios = ftsdc010_set_ios,
350 .get_cd = ftsdc010_get_cd,
351 .get_wp = ftsdc010_get_wp,
352};
353
354#else
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200355static const struct mmc_ops ftsdc010_ops = {
356 .send_cmd = ftsdc010_request,
357 .set_ios = ftsdc010_set_ios,
Rick Chenf7a4adb2017-08-28 16:44:11 +0800358 .getcd = ftsdc010_get_cd,
359 .getwp = ftsdc010_get_wp,
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200360 .init = ftsdc010_init,
361};
Rick Chenf7a4adb2017-08-28 16:44:11 +0800362#endif
363
364void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
365 uint caps, u32 max_clk, u32 min_clk)
366{
367 cfg->name = name;
368 cfg->f_min = min_clk;
369 cfg->f_max = max_clk;
370 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
371 cfg->host_caps = caps;
372 if (buswidth == 8) {
373 cfg->host_caps |= MMC_MODE_8BIT;
374 cfg->host_caps &= ~MMC_MODE_4BIT;
375 } else {
376 cfg->host_caps |= MMC_MODE_4BIT;
377 cfg->host_caps &= ~MMC_MODE_8BIT;
378 }
Rick Chenf7a4adb2017-08-28 16:44:11 +0800379 cfg->part_type = PART_TYPE_DOS;
380 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
381}
382
383void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg)
384{
385 switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) {
386 case FTSDC010_BWR_CAPS_4BIT:
387 cfg->host_caps |= MMC_MODE_4BIT;
388 break;
389 case FTSDC010_BWR_CAPS_8BIT:
390 cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
391 break;
392 default:
393 break;
394 }
395}
396
397#ifdef CONFIG_BLK
398int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
399{
400 return mmc_bind(dev, mmc, cfg);
401}
402#else
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200403
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000404int ftsdc010_mmc_init(int devid)
405{
406 struct mmc *mmc;
407 struct ftsdc010_chip *chip;
408 struct ftsdc010_mmc __iomem *regs;
409#ifdef CONFIG_FTSDC010_BASE_LIST
410 uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST;
411
412 if (devid < 0 || devid >= ARRAY_SIZE(base_list))
413 return -1;
414 regs = (void __iomem *)base_list[devid];
415#else
416 regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
417#endif
418
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000419 chip = malloc(sizeof(struct ftsdc010_chip));
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200420 if (!chip)
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000421 return -ENOMEM;
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000422 memset(chip, 0, sizeof(struct ftsdc010_chip));
423
424 chip->regs = regs;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200425#ifdef CONFIG_SYS_CLK_FREQ
426 chip->sclk = CONFIG_SYS_CLK_FREQ;
427#else
428 chip->sclk = clk_get_rate("SDC");
429#endif
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000430
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200431 chip->cfg.name = "ftsdc010";
Rick Chenf7a4adb2017-08-28 16:44:11 +0800432#ifndef CONFIG_DM_MMC
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200433 chip->cfg.ops = &ftsdc010_ops;
Rick Chenf7a4adb2017-08-28 16:44:11 +0800434#endif
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200435 chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
Rick Chenf7a4adb2017-08-28 16:44:11 +0800436 set_bus_width(regs , &chip->cfg);
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200437 chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
438 chip->cfg.f_max = chip->sclk / 2;
439 chip->cfg.f_min = chip->sclk / 0x100;
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000440
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200441 chip->cfg.part_type = PART_TYPE_DOS;
442 chip->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000443
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200444 mmc = mmc_create(&chip->cfg, chip);
445 if (mmc == NULL) {
446 free(chip);
447 return -ENOMEM;
448 }
Kuo-Jung Sud123ab82013-05-06 20:32:51 +0000449
450 return 0;
451}
Rick Chenf7a4adb2017-08-28 16:44:11 +0800452#endif